MT91L60/61

Data Sheet

8

Zarlink Semiconductor Inc.

Figure 4 - Audio Gain Partitioning

Figure 5 - Serial Port Relative Timing for Motorola Mode 00/National Microwire

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R/W

1)

Delays due to internal processor timing which are transparent.

2)

The MT91L60/L61:latches received data on the rising edge of SCLK.

3)

The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The

4)

A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.

5)

The COMMAND/ADDRESS byte contains:

1)

3)

4)

5)

1)

2)

3)

4)

COMMAND/ADDRESS

DATA INPUT/OUTPUT

COMMAND/ADDRESS:

DATA 1

RECEIVE

DATA 1

TRANSMIT

SCLK

CS

-outputs transmit data on the falling edge of SCLK.

subsequent byte is always data until terminated via CS returning high.

1 bit - Read/Write

3 bits - Addressing Data

4 bits - Unused

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1)

3)

4)

1)

2)

3)

4)

COMMAND/ADDRESS

DATA INPUT/OUTPUT

COMMAND/ADDRESS:

DATA 2

RECEIVE

DATA 1

TRANSMIT

SCLK

CS

R/W

X

1)

Delays due to internal processor timing which are transparent.

3)

The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The

4)

A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.

5)

The COMMAND/ADDRESS byte contains:

subsequent byte is always data until terminated via CS returning high.

1 bit - Read/Write

3 bits - Addressing Data

4 bits - Unused

5)

2)

The MT91L60/L61: latches received data on the rising edge of SCLK.

-outputs transmit data on the falling edge of SCLK.

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