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MC10H640FN Datasheet(PDF) 1 Page - ON Semiconductor

Part # MC10H640FN
Description  68030/040 PECL to TTL Clock Driver
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC10H640FN Datasheet(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 8
1
Publication Order Number:
MC10H640/D
MC10H640, MC100H640
68030/040 PECL to TTL
Clock Driver
Description
The MC10H/100H640 generates the necessary clocks for the
68030, 68040 and similar microprocessors. It is guaranteed to meet the
clock specifications required by the 68030 and 68040 in terms of
part−to−part skew, within−part skew and also duty cycle skew.
The user has a choice of using either TTL or PECL (ECL referenced
to +5.0 V) for the input clock. TTL clocks are typically used in present
MPU systems. However, as clock speeds increase to 50 MHz and
beyond, the inherent superiority of ECL (particularly differential
ECL) as a means of clock signal distribution becomes increasingly
evident. The H640 also uses differential PECL internally to achieve its
superior skew characteristic.
The H640 includes divide−by−two and divide−by−four stages, both
to achieve the necessary duty cycle skew and to generate MPU clocks
as required. A typical 50 MHz processor application would use an
input clock running at 100 MHz, thus obtaining output clocks at
50 MHz and 25 MHz (see Logic Diagram).
Features
Generates Clocks for 68030/040
Meets 030/040 Skew Requirements
TTL or PECL Input Clock
Extra TTL and PECL Power/Ground Pins
Asynchronous Reset
Single +5.0 V Supply
Pb−Free Packages are Available*
Function
Reset (R): LOW on RESET forces all Q outputs LOW and all Q
outputs HIGH.
Power−Up:The device is designed to have the POS edges of the ÷ 2
and ÷ 4 outputs synchronized at power up.
Select (SEL): LOW selects the ECL input source (DE/DE). HIGH
selects the TTL input source (DT).
The H640 also contains circuitry to force a stable state of the ECL
input differential pair, should both sides be left open. In this case, the
DE side of the input is pulled LOW, and DE goes HIGH.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
MARKING DIAGRAM*
xxx
= 10 or 100
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G= Pb−Free Package
PLCC−28
FN SUFFIX
CASE 776
MCxxxH640G
AWLYYWW
1
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION


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