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TMS320C32PCM60 Datasheet(PDF) 10 Page - Texas Instruments |
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TMS320C32PCM60 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 45 page  TMS320C32 DIGITAL SIGNAL PROCESSOR SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 external memory interface (continued) D For 32-bit-wide physical memory, all STRB0 and STRB1 pins function as byte-enable (chip-select) pins. See Figure 4. STRB0_B2/A –2 CS A14 A13 A2 A1 A0 Data CS Data A14 A13 A2 A1 A0 STRB0_B3/A –1 CS Data A2 A13 A14 A0 A1 32-Bit Data Bus CS Data A0 A1 A2 A13 A14 STRB0_B0 STRB0_B1 A0 A1 A2 A13 A14 Data . . . . . . . . . . 8 8 8 8 32 Figure 4. ’C32 With 32-Bit-Wide External Memory For more detailed information and examples see TMS320C32 Addendum to the TMS320C3x User’s Guide (literature number SPRU132) and Interfacing Memory to the TMS320C32 DSP Application Report (literature number SPRA040). D The IOSTRB control signal, like STRB0 and STRB1, also is mapped to a specific range of addresses but it is a single signal that can access only 32-bit data from 32-bit-wide memory. Its range of addresses appears in the TMS320C32 memory map, shown in Figure 8. The IOSTRB bus timing is different from the STRB0 and STRB1 bus timings to accommodate slower I/O peripherals. |
Similar Part No. - TMS320C32PCM60 |
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Similar Description - TMS320C32PCM60 |
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