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SN74GTL16616DLG4 Datasheet(PDF) 8 Page - Texas Instruments |
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SN74GTL16616DLG4 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 14 page www.ti.com Timing Requirements SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCBS481H – JUNE 1994 – REVISED APRIL 2005 over recommended ranges of supply voltage and operating free-air temperature, V TT = 1.5 V and VREF = 1 V for GTL+ (unless otherwise noted) (see Figure 1) MIN MAX UNIT fclock Clock frequency 95 MHz LEAB or LEBA high 3.3 tw Pulse duration ns CLKAB or CLKBA high or low 5.5 A before CLKAB ↑ 1.3 B before CLKBA ↑ 2.3 A before LEAB ↓ 0 tsu Setup time ns B before LEBA ↓ 1.3 CEAB before CLKAB ↑ 2.2 CEBA before CLKBA ↑ 2.7 A after CLKAB ↑ 1.6 B after CLKBA ↑ 0.6 A after LEAB ↓ 4 th Hold time ns B after LEBA ↓ 3.5 CEAB after CLKAB ↑ 1.1 CEBA after CLKBA ↑ 0.9 8 |
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