SN54LVT8980, SN74LVT8980

EMBEDDED TEST BUS CONTROLLERS

IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8BIT GENERIC HOST INTERFACES

SCBS676E − DECEMBER 1996 − REVISED MARCH 2004

10

POST OFFICE BOX 655303

host access timing (continued)

For write access (R/W low), the eTBC data outputs remain at high impedance independent of STRB. The

address of the register to be written is latched from the address pins on the falling edge of STRB, while the data

to be written is latched from the data bus on the rising edge of STRB.

tPHL

th

th

STRB

RDY

R/W

D

A

tsu

tsu

Valid

tPLH

tPZH or tPZL

tPHZ or tPLZ

Figure 6. Read Access Timing

th

tPHL

th

th

STRB

RDY

R/W

D

A

tsu

tsu

Valid

tPLH

tsu

Valid

Figure 7. Write Access Timing