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DSP56004FJ50 Datasheet(PDF) 3 Page - Freescale Semiconductor, Inc |
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DSP56004FJ50 Datasheet(HTML) 3 Page - Freescale Semiconductor, Inc |
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3 / 82 page  DSP56004 Features MOTOROLA DSP56004/D, Rev. 3 iii FEATURES Digital Signal Processing Core • Efficient, object code compatible with the 24-bit DSP56000 core engine • Up to 40.5 Million Instructions Per Second (MIPS)—24.7 ns instruction cycle at 81 MHz; up to 324 Million Operations Per Second (MOPS) at 81 MHz • Highly parallel instruction set with unique DSP addressing modes • Two 56-bit accumulators including extension byte • Parallel 24 × 24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles) • Double precision 48 × 48-bit multiply with 96-bit result in 6 instruction cycles • 56-bit addition/subtraction in 1 instruction cycle • Fractional and integer arithmetic with support for multiprecision arithmetic • Hardware support for block floating-point Fast Fourier Transforms (FFT) • Hardware nested DO loops • Zero-overhead fast interrupts (2 instruction cycles) • Four 24-bit internal data buses and three 16-bit internal address buses for simultaneous accesses to one program and two data memories • Fabricated in high-density CMOS Memory • On-chip modified Harvard architecture which permits simultaneous accesses to program and two data memories • Bootstrap loading from Serial Host Interface or External Memory Interface Table 1 Memory Configuration (Word width is 24 bits) Part Type Program X Data Y Data Boot-strap ROM ROM RAM ROM RAM ROM RAM DSP560041 None 512 256 256 256 256 64 DSP56004ROM2 2560 256 256 256 256 256 64 Note: 1. X data ROM is programmed with log2x and 2 x tables; Y data ROM is programmed with a sine table. 2. These ROMs may be factory programmed with data/program provided by the application developer. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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