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HD74LS165AFPEL Datasheet(PDF) 5 Page - Renesas Technology Corp |
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HD74LS165AFPEL Datasheet(HTML) 5 Page - Renesas Technology Corp |
5 / 8 page HD74LS165A Rev.3.00, Jul.15.2005, page 5 of 7 Waveforms 2 Clock Inhibit Input Clock Input F and H Inputs (See Notes A and B) (Disable while clock is high) Shift/ Load Output QH Output QH 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tw (clock) tw (load) tw (load) tsu tsu tsu VOH VOL VOH VOL 0V 3V 0V 3V 0V 3V 0V 3V Notes: A. The remaining six data inputs and the serial input are low. B. Prior to test, high-level data is loaded into H input. C. The input pulse Generators have the following characteristics: PRR ≤ 1 MHz, duty cycle ≤ 50%, Z out ≈ 50 Ω, t TLH ≤ 15 ns, t THL ≤ 6 ns. |
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