ADS7808

6

SBAS018A

www.ti.com

HEX

HEX

DESCRIPTION

BINARY CODE

CODE

BINARY CODE

CODE

Full-Scale Range

±10

±5

±3.33V

0V to 5V

0V to 10V

0V to 4V

Least Significant Bit (LSB)

4.88mV

2.44mV

1.63mV

1.22mV

2.44mV

0.98mV

+Full Scale (FS – 1LSB)

9.99512V 4.99756V 3.33171V

4.99878V 9.99756V

3.99902V

0111 1111 1111

7FF

1111 1111 1111

FFF

Midscale

0V

0V

0V

2.5V

5V

2V

0000 0000 0000

000

1000 0000 0000

800

One LSB Below Midscale

–4.88mV

–2.44mV

–1.63mV

2.49878V 4.99756V

1.99902V

1111 1111 1111

FFF

0111 1111 1111

7FF

–Full Scale

–10V

–5V

–3.333333V

0V

0V

0V

1000 0000 0000

800

0000 0000 0000

000

BINARY TWO’S

COMPLEMENT

STRAIGHT BINARY

(SB/BTC LOW)

(SB/BTC HIGH)

Initiate Conversion and

Output Data Using External

Clock

Power Down

Selecting Output Format

Incorrect Conversions

SPECIFIC FUNCTION

CS

R/C

BUSY

EXT/INT DATACLK PWRD

SB/BTC

OPERATION

Initiate Conversion and

1>0

0

1

0

Output

0

x

Initiates conversion “n”. Data from conversion “n–1”

Output Data Using

clocked out on DATA synchronized to 12 clock

Internal Clock

pulses output on DATACLK.

0

1>0

1

0

Output

0

x

Initiates conversion “n”. Data from conversion “n–1”

clocked out on DATA synchronized to 12 clock

pulses output on DATACLK.

1>0

0

1

1

Input

0

x

Initiates conversion “n”.

0

1>0

1

1

Input

0

x

Initiates conversion “n”.

1>0

1

1

1

Input

x

x

Outputs a pulse on SYNC followed by data from

conversion “n” clocked out synchronized to external

DATACLK.

1>0

1

0

1

Input

0

x

Outputs a pulse on SYNC followed by data from

conversion “n–1” clocked out synchronized to

0

0>1

0

1

Input

0

x

Outputs a pulse on SYNC followed by data from

conversion “n–1” clocked out synchronized to

0

0

0>1

x

x

0

x

CS or R/C must be HIGH or a new conversion will

be initiated without time for acquisition.

x

x

x

x

x

0

x

Analog circuitry powered. Conversion can proceed.

x

x

x

x

x

1

x

Analog circuitry disabled. Data from previous

conversion maintained in output registers.

x

x

x

x

x

x

0

Serial data is output in Binary Two’s Complement

format.

x

x

x

x

x

x

1

Serial data is output in Straight Binary format.

NOTE: (1) See Figure 3b for constraints on previous data valid during conversion.

Table III. Control Truth Table.

ANALOG INPUT

DIGITAL OUTPUT

Table IV. Output Codes and Ideal Input Voltages.