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ZL50235GD Datasheet(PDF) 10 Page - Zarlink Semiconductor Inc |
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ZL50235GD Datasheet(HTML) 10 Page - Zarlink Semiconductor Inc |
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10 / 43 page  ZL50235 Data Sheet 10 Zarlink Semiconductor Inc. 2.0 Device Overview The ZL50235 architecture contains 16 echo cancellers divided into 8 groups. Each group has two echo cancellers, Echo Canceller A and Echo Canceller B. Each group can be configured in Normal, Extended Delay or Back-to- Back configurations. In Normal configuration, a group of echo cancellers provides two channels of 64 ms echo cancellation, which run independently on different channels. In Extended Delay configuration, a group of echo cancellers achieves 128 ms of echo cancellation by cascading the two echo cancellers (A & B). In Back-to-Back configuration, the two echo cancellers from the same group are positioned to cancel echo coming from both directions in a single channel, providing full-duplex 64 ms echo cancellation. Each echo canceller contains the following main elements (see Figure 4). • Adaptive Filter for estimating the echo channel • Subtractor for cancelling the echo • Double-Talk detector for disabling the filter adaptation during periods of double-talk • Path Change detector for fast reconvergence on major echo path changes • Instability Detector to combat instability in very low ERL environments • Patented Advanced Non-Linear Processor for suppression of residual echo, with comfort noise injection • Disable Tone Detectors for detecting valid disable tones at send and receive path inputs • Narrow-Band Detector for preventing Adaptive Filter divergence from narrow-band signals • Offset Null filters for removing the DC component in PCM channels • +9 to -12 dB level adjusters at all signal ports • Parallel controller interface compatible with Motorola microcontrollers • PCM encoder/decoder compatible with µ/A-Law ITU-T G.711 or Sign-Magnitude coding Each echo canceller in the ZL50235 has four functional states: Mute, Bypass, Disable Adaptation and Enable Adaptation. These are explained in the section entitled Echo Canceller Functional States. Figure 4 - Functional Block Diagram Σ Non-Linear Processor Offset Null Linear/ µ/A-Law Microprocessor Interface Double - Talk Detector Narrow-Band Detector µ/A-Law/ Linear Offset Null Echo Canceller (N), where 0 < N < 15 Sout Rin Sin Rout - Programmable Bypass (channel N) (channel N) (channel N) (channel N) MuteR MuteS +9 to -12 dB Level Adjust Linear/ µ/A-Law +9 to -12 dB Level Adjust +9 to -12 dB Level Adjust µ/A-Law/ Linear +9 to -12 dB Level Adjust Disable Tone Detector Disable Tone Detector Detector Path Change Instability Detector |
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