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ZL50233QC Datasheet(PDF) 5 Page - Zarlink Semiconductor Inc |
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ZL50233QC Datasheet(HTML) 5 Page - Zarlink Semiconductor Inc |
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5 / 38 page  ZL50233 Data Sheet 5 Zarlink Semiconductor Inc. DS R11 10 Data Strobe (Input). This active low input works in conjunction with CS to enable the read and write operations. CS R13 11 Chip Select (Input). This active low input is used by a microprocessor to activate the microprocessor port. R/W R5 12 Read/Write (Input). This input controls the direction of the data bus lines (D7-D0) during a microprocessor access. DTA R7 13 Data Transfer Acknowledgment (Open Drain Output). This active low output indicates that a data bus transfer is completed. A pull-up resistor (1 K typical) is required at this output. D0..D7 T2,T4,T6,T8,T9,T11, T13,T15 15, 16, 17, 19, 20, 21, 22, 23 Data Bus D0 - D7 (Bidirectional). These pins form the 8 bit bidirectional data bus of the microprocessor port. A0..A10 P16,N16,M16,L16,K16, J16,H16,G16,F16,E16, D16 28, 29, 30, 31, 33, 34, 35, 36, 38, 39, 40 Address A0 to A10 (Input). These inputs provide the A10 - A0 address lines to the internal registers. ODE B13 57 Output Drive Enable (Input). This input pin is logically AND’d with the ODE bit-6 of the Main Control Register. When both ODE bit and ODE input pin are high, the Rout and Sout ST-BUS outputs are enabled. When the ODE bit is low or the ODE input pin is low, the Rout and Sout ST-BUS outputs are high impedance. Sout A8 58 Send PCM Signal Output (Output). Port 1 TDM data output streams. Sout pin outputs serial TDM data streams at 2.048 Mbps with 4 channels per stream. Rout B9 59 Receive PCM Signal Output (Output). Port 2 TDM data output streams. Rout pin outputs serial TDM data streams at 2.048 Mbps with 4 channels per stream. Sin B11 60 Send PCM Signal Input (Input). Port 2 TDM data input streams. Sin pin receives serial TDM data streams at 2.048 Mbps with 4 channels per stream. Rin B7 61 Receive PCM Signal Input (Input). Port 1 TDM data input streams. Rin pin receives serial TDM data streams at 2.048 Mbps with 4 channels per stream. F0i B5 62 Frame Pulse (Input). This input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS or GCI interface specifications. C4i A4 63 Serial Clock (Input). 4.096 MHz serial clock for shifting data in/out on the serial streams (Rin, Sin, Rout, Sout). MCLK G2 90 Master Clock (Input). Nominal 10 MHz or 20 MHz Master Clock input. May be connected to an asynchronous (relative to frame signal) clock source. Pin Description (continued) Pin Name Pin # Description 208-Ball LBGA 100 Pin LQFP |
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Similar Description - ZL50233QC |
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