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ZL50211GBG2 Datasheet(PDF) 8 Page - Zarlink Semiconductor Inc

Part # ZL50211GBG2
Description  256 Channel Voice Echo Canceller
Download  42 Pages
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Manufacturer  ZARLINK [Zarlink Semiconductor Inc]
Direct Link  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

ZL50211GBG2 Datasheet(HTML) 8 Page - Zarlink Semiconductor Inc

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ZL50211
Data Sheet
8
Zarlink Semiconductor Inc.
IRQ1, IRQ2, IRQ3,
IRQ4, IRQ5, IRQ6,
IRQ7, IRQ8
User
Signals
N4,AJ26,N3,AK5,
AJ6,AG23,L30,L29
Interrupt Request (Open Drain Output). These
outputs go low when an interrupt occurs in any
channel. Each IRQ returns high when all the interrupts
have been read from the Interrupt FIFO Register of
respective EVP. A pull-up resistor (1 K typical) is
required at these outputs.
Extra Device Pins
-
W3,E15,V4,AK16,
AK15,AK14,D13,
C13,V3,A12,B13,
AK13,AH14,U3,V2,
AJ14
No connection. The ball pins must be left open for
normal operation.
JTAG SIGNAL PINS
TMS
JTAG
Signal
K2
Test Mode Select (3.3 V Input). JTAG signal that
controls the state transitions of the TAP controller. This
pin is pulled high by an internal pull-up when not
driven. This signal is connected to all processors.
TCK
JTAG
Signal
D6
Test Clock (3.3 V Input). Provides the clock to the
JTAG test logic.This signal is connected to all
processors.
TRST
JTAG
Signal
D7
Test Reset (3.3 V Input). Asynchronously initializes
the JTAG TAP controller by putting it in the Test-Logic-
Reset state. This pin should be pulsed low on power-
up or held low, to ensure that all the EVP’s are in the
normal functional mode. This pin is pulled by an
internal pull-down when not driven. This signal is
connected to all EVP’s.
TDI1,TDI2,TDI3,TDI4,
TDI5,TDI6,TDI7,TDI8
JTAG
Signals
K1,AK23,L2,AK2,
AJ3,AH20,F27,H27
Test Serial Data In (3.3 V Input). JTAG serial test
instructions and data are shifted in on these pins.
These pins are pulled high by an internal pull-up when
not driven.
TDO1,TDO2,TDO3,
TDO4,TDO5,TDO6
TDO7,TDO8
JTAG
Signals
L1,AJ22,L4,AH4,
AK3,AK24,J28,K28
Test Serial Data Out (Output). JTAG serial data is
outputted on these pins on the falling edge of TCK.
These pins are held in high impedance state when
JTAG scan is not enabled.
PLL SIGNAL PINS
PLLVDD2 = 1.8V
PLL
Power
H3,V1,H4,AE3,
AG2,AE26,D22,
C24, AE27
PLL Power Supply. Must be connected to PLLVDD2 =
1.8V.
PLLVSS1
PLLVSS2
PLL
Power
J3,W2,H2,AF4,
AF3,AF27,D24,
C25,AF26,H1,W4,
J2, AH1,AG3,AF22,
D25,E27,AF21
PLL Ground. Must be connected to VSS.
Signal Name
Signal
Type
BGA Ball #
Signal Description


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