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ZL50020QCG1 Datasheet(PDF) 5 Page - Zarlink Semiconductor Inc |
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ZL50020QCG1 Datasheet(HTML) 5 Page - Zarlink Semiconductor Inc |
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5 / 83 page  ZL50020 Data Sheet List of Figures 5 Zarlink Semiconductor Inc. Figure 1 - ZL50020 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - ZL50020 256-Ball 17 mm x 17 mm PBGA (as viewed through top of package) . . . . . . . . . . . . . . . . . . . 8 Figure 3 - ZL50020 256-Lead 28 mm x 28 mm LQFP (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4 - Input Timing when CKIN1 - 0 bits = “10” in the CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 5 - Input Timing when CKIN1 - 0 bits = “01” in the CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 6 - Input Timing when CKIN1 - 0 = “00” in the CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 7 - Output Timing for CKo0 and FPo0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 8 - Output Timing for CKo1 and FPo1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 9 - Output Timing for CKo2 and FPo2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 10 - Output Timing for CKo3 and FPo3 with CKoFPo3SEL1-0=”11” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 11 - Input Bit Delay Timing Diagram (ST-BUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 12 - Input Bit Sampling Point Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 13 - Input Bit Delay and Factional Sampling Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 14 - Output Bit Advancement Timing Diagram (ST-BUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 15 - Output Fractional Bit Advancement Timing Diagram (ST-BUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 16 - Channel Switching External High Impedance Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 17 - Data Throughput Delay for Variable Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 18 - Data Throughput Delay for Constant Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 19 - Timing Parameter Measurement Voltage Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 20 - Motorola Non-Multiplexed Bus Timing - Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 21 - Motorola Non-Multiplexed Bus Timing - Write Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 22 - Intel Non-Multiplexed Bus Timing - Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 23 - Intel Non-Multiplexed Bus Timing - Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 24 - JTAG Test Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 25 - Frame Pulse Input and Clock Input Timing Diagram (ST-BUS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure 26 - Frame Pulse Input and Clock Input Timing Diagram (GCI-Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure 27 - ST-BUS Input Timing Diagram when Operated at 2, 4, 8 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 28 - ST-BUS Input Timing Diagram when Operated at 16 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 29 - GCI-Bus Input Timing Diagram when Operated at 2, 4, 8 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 30 - GCI-Bus Input Timing Diagram when Operated at 16 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 31 - ST-BUS Output Timing Diagram when Operated at 2, 4, 8 or 16 Mbps . . . . . . . . . . . . . . . . . . . . . . . 73 Figure 32 - GCI-Bus Output Timing Diagram when Operated at 2, 4, 8 or 16 Mbps . . . . . . . . . . . . . . . . . . . . . . . 73 Figure 33 - Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 34 - Output Drive Enable (ODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 35 - Input and Output Frame Boundary Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 36 - FPo0 and CKo0 Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 37 - FPo1 and CKo1 Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Figure 38 - FPo2 and CKo2 Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Figure 39 - FPo3 and CKo3 Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Figure 40 - Output Timing (ST-BUS Format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 |
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