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ZL50015QCG1 Datasheet(PDF) 11 Page - Zarlink Semiconductor Inc |
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ZL50015QCG1 Datasheet(HTML) 11 Page - Zarlink Semiconductor Inc |
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11 / 81 page  ZL50016 Data Sheet 11 Zarlink Semiconductor Inc. K3 234 TMS Test Mode Select (5 V-Tolerant Input with Internal Pull-up) JTAG signal that controls the state transitions of the TAP controller. This pin is pulled high by an internal pull-up resistor when it is not driven. L4 238 TCK Test Clock (5 V-Tolerant Schmitt-Triggered Input with Internal Pull-up) Provides the clock to the JTAG test logic. L3 239 TRST Test Reset (5 V-Tolerant Input with Internal Pull-up) Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be pulsed low during power-up to ensure that the device is in the normal functional mode. When JTAG is not being used, this pin should be pulled low during normal operation. M3 240 TDi Test Serial Data In (5 V-Tolerant Input with Internal Pull-up) JTAG serial test instructions and data are shifted in on this pin. This pin is pulled high by an internal pull-up resistor when it is not driven. G5 212 TDo Test Serial Data Out (5 V-Tolerant Three-state Output) JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG is not enabled. B12, B13, C10, C11, F13, G4, K12, C12, 80, 105, 150, 151, 152, 153, 210, 149 IC_Open Internal Test Mode (5 V-Tolerant Input with Internal Pull-down) These pins may be left unconnected. G3, D12, B14, C13 144, 107, 148, 208 IC_GND Internal Test Mode Enable (5 V-Tolerant Input) These pins MUST be low. PBGA Pin Number LQFP Pin Number Pin Name Description |
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