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ZL40510LDG Datasheet(PDF) 7 Page - Zarlink Semiconductor Inc |
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ZL40510LDG Datasheet(HTML) 7 Page - Zarlink Semiconductor Inc |
7 / 30 page ZL40510/14 Data Sheet 7 Zarlink Semiconductor Inc. 1.5 Specified Electrical Performance with 15 mm Interconnect and Zarlink ZLE40510/14 Evaluation Board The specified performance in the table are results based on the electrical measurements and simulations across full process corners using the Zarlink Evaluation Board using a 3.9 Ohm resistive load to ground. The track interconnect between ZL40510/14 and the 3.9 Ohm Resistor is 15 mm long and uses a 2 mm wide track on single sided FR4 board. The return path is via two 2 mm wide tracks spaced 0.25 mm either side of the track between output and the 3.9 Ohm resistor. The combined forward and return path forms a co planar transmission line with a characteristic impedance of approximately 120 Ohms. The tight coupled return paths carrying the return current reduce the effective series inductance (Leff) which can be approximated to: Leff = 2 * Lint * (1 - K) + 2 * Lfix * (1 - K). The ZLE40510 board has two positions for the Laser Diode at two different distances. (15 and 30 mm). • The measured value of Leff is 7 nH • The estimated value of Leff = 2 * 8 (1 – 0.5) = 8 nH The actual pulse response achieved in an application is thus dependent on the application. 1.6 Application Layout Guide Lines Minimize interconnect inductance by: a. Using Short Interconnect Distance b. Use wide interconnect tracks c. Keep the return path tightly coupled to the forward path. |
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