ZL38010

Data Sheet

3

Zarlink Semiconductor Inc.

5BCLK

Bit Clock (Input). 128 kHz to 4096 kHz bit clock input for both PCM and ADPCM ports;

used in SSI mode only. The falling edge of this clock latches data into ADPCMi, PCMi1

and PCMi2. The rising edge clocks data out on ADPCMo, PCMo1 and PCMo2. This input

6PCMo1

Serial PCM Stream 1 (Output). 128 kbps to 4096 kbps serial companded/linear PCM out-

put stream. Data are clocked out by rising edge of BCLK in SSI mode. Clocked out by

MCLK divided by two in ST-BUS mode. See Figure 14.

7PCMi1

Serial PCM Stream 1 (Input). 128 kbps to 4096 kbps serial companded/linear PCM

input stream. Data are clocked in on falling edge of BCLK in SSI mode. Clocked in at the

3/4 bit position of MCLK in ST-BUS mode. See Figure 14.

Digital Ground. Nominally 0 volts

9

LINEAR

bit linear PCM. Linear PCM operates only at a bit rate of 2048 kbps. Companded PCM is

10

ENB2/F0od

PCM B-Channel Enable Strobe 2 (Input) / Delayed Frame Pulse (Output).

SSI operation: ENB2 (Input). An 8-bit wide enable strobe input defining B2 channel

(AD)PCM data. A valid 8-bit strobe must be present at this input for SSI operation. See

Figure 4 & Figure 6.

ST-BUS operation: F0od (Output). This pin is a delayed frame strobe output. When LIN-

EAR=0, this becomes a delayed frame pulse output occurring 64 C4 clock cycles after

F0i and when LINEAR = 1 at 128 C4 clock cycles after F0i. See Figures 7, 8, 9 & 14.

11

ENB1

PCM B-Channel Enable Strobe 1 (Input).

SSI operation: An 8-bit wide enable strobe input defining B1 channel (AD)PCM data. A

valid 8-bit strobe must be present at this input for SSI operation.

are forced to a high-impedance state.

12

PCMo2

Serial PCM Stream 2 (Output). 128 kbps to 4096 kbps serial companded/linear PCM out-

put stream. Clocked out by rising edge of BCLK in SSI mode. Clocked out by MCLK divid-

ed by two in ST-BUS mode. See Figure 14.

13

PCMi2

Serial PCM Stream 2 (Input). 128 kbps to 4096 kbps serial companded/linear PCM input

stream. Data bits are clocked in on falling edge of BCLK in SSI mode. Clocked in at the

3/4 bit position of MCLK in ST-BUS mode. See Figure 14.

14

SEL

SELECT (Input).

PCM bypass mode: When SEL=0 the PCM1 port is selected for PCM bypass operation

and when SEL=1 the PCM2 port is selected for PCM bypass operation.

See Figure 6 & Figure 9.

16 kbps transcoding mode:

SSI Operation - in 16 kbps transcoding mode, the ADPCM words are assigned to the I/O

timeslot defined by ENB2 when SEL=1 and by ENB1 when SEL=0. See Figure 4.

ST-BUS operation- in 16 kbps transcoding mode, the ADPCM words are assigned to the

B2 timeslot when SEL=1 and to the B1 timeslot when SEL=0. See Figure 9.

Pin #

Name

Description