ZL38010

Data Sheet

2

Zarlink Semiconductor Inc.

Switching, on-the-fly, between 32 kbps and 24 kbps ADPCM, is possible by controlling the appropriate mode select

(MS1 - MS6) control pins. All optional functions of the device are pin selectable allowing a simple interface to

industry standard codecs, digital phone devices and Layer 1 transceivers. Linear coded PCM is provided to

facilitate external DSP functions.

Change Summary

Changes from October 2005 Issue to January 2007 Issue.

Figure 2 - Pin Connections

Pin Description

Page

Item

Change

1

Ordering Information Box

Added Pb Free part numbers.

Pin #

Name

Description

1EN1

Enable Strobe 1 (Output). This 8 bit wide, active high strobe is active during the B1

PCM channel in ST-BUS mode. Becomes a single bit, high true pulse when LINEAR=1.

In SSI mode this output is high impedance.

2MCLK

Master Clock (input). This is a 4.096 MHz (minimum) input clock utilized by the

transcoder function; it must be supplied in both ST-BUS and SSI modes of operation.

In ST-BUS mode the C4 ST-BUS clock is applied to this pin. This synchronous clock is

also used to control the data I/O flow on the PCM and ADPCM input/output pins

according to ST-BUS requirements.

In SSI mode this master clock input is derived from an external source and may be

asynchronous with respect to the 8 kHz frame. MCLK rates greater than 4.096 MHz are

acceptable in this mode since the data I/O rate is governed by BCLK.

3F0i

Frame Pulse (Input). Frame synchronization pulse input for ST-BUS operation. SSI

4C2o

2.048 MHz Clock (Output). This ST-BUS mode bit clock output is the MCLK (C4) input

divided by two, inverted, and synchronized to F0i. This output is high-impedance during

SSI operation.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

28

27

26

25

24

23

22

21

MS1

VDD

MS3

IC

MS4

FORMAT

MS2

PWRDN

ADPCMi

ADPCMo

MS5

MS6

EN2

PCMo1

BCLK

PCMi1

LINEAR

ENB2/F0od

VSS

C2o

MCLK

F0i

PCMi2

ENB1

PCMo2

EN1

SEL

A/

µ