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ZL30410QCG1 Datasheet(PDF) 8 Page - Zarlink Semiconductor Inc |
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ZL30410QCG1 Datasheet(HTML) 8 Page - Zarlink Semiconductor Inc |
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8 / 39 page  ZL30410 Data Sheet 8 Zarlink Semiconductor Inc. 36 Tclk IEEE1149.1a Test Clock Signal (5 V tolerant input). Input clock for the JTAG test logic. If not used, this pin should be pulled up to VDD. 37 Trst IEEE1149.1a Reset Signal (3.3 V input). Asynchronous reset for the JTAG TAP controller. This pin should be pulsed low on power-up to ensure that the device is in the normal functional state. This pin is internally pulled up to VDD. If this pin is not used then it should be connected to GND. 38 Tdi IEEE1149.1a Test Data Input (3.3 V input). Input for JTAG serial test instructions and data. This pin is internally pulled up to VDD. If not used, this pin should be left unconnected. 39 NC No internal bonding Connection. Leave unconnected. 40 NC No internal bonding Connection. Leave unconnected. 41 PRIOR Primary Reference Out of Range (Output). Logic high at this pin indicates that the Primary Reference is off the PLL centre frequency by more than ±12 ppm. See PRIOR pin description in Section 4.2 on page 17 for details. 42 C1.5o Clock 1.544 MHz (CMOS tristate output). This output provides a 1.544 MHz DS1 rate clock. 43 C6o Clock 6.312 MHz (CMOS tristate output). This output provides a 6.312 MHz DS2 rate clock. 44 IC Internal Connection. Connect this pin to Ground. 45 GND Ground 46 C19o Clock 19.44 MHz (CMOS tristate output). This output provides a 19.44 MHz clock. 47 RefSel Reference Source Select (Input). A logic low selects the PRI (primary) reference source as the input reference signal and logic high selects the SEC (secondary) input. The logic level at this input is sampled at the rising edge of F8o. This pin is internally pulled down to GND. 48 RefAlign Reference Alignment (Input). In Hardware Control pulling this pin low for 250 µs initiates phase realignment between the input reference and the generated output clocks. See Section 3.2.4 on page 11 for details. This pin should never be tied low permanently. Internally this pin is pulled down to GND. 49 VDD Positive Power Supply 50 NC No internal bonding Connection. Leave unconnected. 51 C20i Clock 20 MHz (5 V tolerant input). This pin is the input for the 20 MHz Master Clock Oscillator. The clock oscillator should be connected directly (not AC coupled) to the C20i input and it must supply clock with duty cycle that is not worse than 40/60%. 52 GND Digital Ground Pin Description (continued) Pin # Name Description |
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