TAS5012

SLES006A – SEPTEMBER 2001 – REVISED DECEMBER 2001

11

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functional description (continued)

MSB left-justified serial interface format (for 16 bits)

MSB

LSB

MSB

LSB

SCLK

LRCLK = Fs

SDIN

Left Channel

Right Channel

Figure 9. MSB Left-Justified Serial Interface Format

Note the following characteristics of this protocol:

DSP compatible serial interface format (for 16 bits)

SCLK

LRCLK = Fs

SDIN

Left Channel

(MSB = 15)

Right Channel

(MSB = 15)

15

14

13

0

15

14

13

0

Figure 10. DSP Compatible Serial Interface Format

Note the following characteristic of this protocol:

PWM Outputs

Designed to be used with the TAS5110 family of H-bridges, the PWM outputs provide differential 3.3-V square-wave

signals. During normal operation these outputs represent the input PCM audio in the pulse-width modulation scheme.

In the hard-mute state the P outputs (PWM_AP_L, PWM_BP_L, PWM_AP_R, and PWM_BP_R) are held low and

the M outputs (PWM_AM_L, PWM_BM_L, PWM_AM_R, and PWM_BM_R) are held high. In the quiet-mute state

the differential PWM outputs have a 50% duty cycle.