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SST34HF1681J-70-4E-LSE Datasheet(PDF) 1 Page - Silicon Storage Technology, Inc |
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SST34HF1681J-70-4E-LSE Datasheet(HTML) 1 Page - Silicon Storage Technology, Inc |
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1 / 37 page  ©2006 Silicon Storage Technology, Inc. S71336-00-000 8/06 1 The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. CSF and ComboMemory are trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. Data Sheet FEATURES: • Flash Organization: 1M x16 or 2M x8 • Dual-Bank Architecture for Concurrent Read/Write Operation – Bottom Sector Protection – 16 Mbit: 12 Mbit + 4 Mbit • PSRAM Organization: – 4 Mbit: 256K x16 – 8 Mbit: 512K x16 • Single 2.7-3.3V Read and Write Operations • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption: – Active Current: 25 mA (typical) – PSRAM Standby Current: 40 µA (typical) • Hardware Sector Protection (WP#) – Protects 4 outer most sectors (4 KWord) in the larger bank by holding WP# low and unprotects by holding WP# high • Hardware Reset Pin (RST#) – Resets the internal state machine to reading data array • Byte Selection for Flash (CIOF pin) – Selects 8-bit or 16-bit mode (56-ball package only) • Sector-Erase Capability – Uniform 2 KWord sectors • Block-Erase Capability – Uniform 32 KWord blocks • Read Access Time – Flash: 70 ns – PSRAM: 70 ns • Erase-Suspend / Erase-Resume Capabilities • Security ID Feature – SST: 128 bits – User: 128 bits • Latched Address and Data • Fast Erase and Program (typical): – Sector-Erase Time: 18 ms – Block-Erase Time: 18 ms – Chip-Erase Time: 35 ms – Program Time: 7 µs • Automatic Write Timing – Internal VPP Generation • End-of-Write Detection – Toggle Bit – Data# Polling – Ready/Busy# pin • CMOS I/O Compatibility • JEDEC Standard Command Set • Packages Available – 56-ball LFBGA (8mm x 10mm) – 62-ball LFBGA (8mm x 10mm) • All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION The SST34HF16x1J ComboMemory devices integrate either a 1M x16 or 2M x8 CMOS flash memory bank with either a 256K x16, or 512K x16 CMOS pseudo SRAM (PSRAM) memory bank in a multi-chip package (MCP). These devices are fabricated using SST’s proprietary, high- performance CMOS SuperFlash technology incorporating the split-gate cell design and thick-oxide tunneling injector to attain better reliability and manufacturability compared with alternate approaches. The SST34HF16x1J devices are ideal for applications such as cellular phones, GPS devices, PDAs, and other portable electronic devices in a low power and small form factor system. The SST34HF16x1J feature dual flash memory bank architecture allowing for concurrent operations between the two flash memory banks and the PSRAM. The devices can read data from either bank while an Erase or Program operation is in progress in the opposite bank. The two flash memory banks are partitioned into 12 Mbit and 4 Mbit with bottom sector protection options for storing boot code, pro- gram code, configuration/parameter data and user data. The SuperFlash technology provides fixed Erase and Pro- gram times, independent of the number of Erase/Program cycles that have occurred. Therefore, the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Pro- gram cycles. The SST34HF16x1J devices offer a guaran- teed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. With high-performance Program operations, the flash memory banks provide a typical Pro- gram time of 7 µsec. The entire flash memory bank can be erased and programmed word-by-word in typically 4 sec- onds for the SST34HF16x1J, when using interface fea- tures such as Toggle Bit, Data# Polling, or RY/BY# to 16 Mbit Concurrent SuperFlash + 4/8 Mbit PSRAM ComboMemory SST34HF1641J / SST34HF1681J SST34HF168116Mb CSF (x8/x16) + 2/4/8 Mb SRAM (x16) MCP ComboMemory |
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