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ZL30402 Datasheet(PDF) 1 Page - Zarlink Semiconductor Inc |
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ZL30402 Datasheet(HTML) 1 Page - Zarlink Semiconductor Inc |
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1 / 44 page  1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved. Features • Meets requirements of GR-253 for SONET stratum 3 and SONET Minimum Clocks (SMC) • Meets requirements of GR-1244 for stratum 3 • Meets requirements of G.813 Option 1 and 2 for SDH Equipment Clocks (SEC) • Generates clocks for ST-BUS, DS1, DS2, DS3, OC-3, E1, E2, E3, STM-1 and 19.44 MHz • Holdover accuracy to 1x10 -12 meets GR-1244 Stratum 3E and ITU-T G.812 requirements • Continuously monitors Primary and Secondary reference clocks • Provides “hit-less” reference switching • Compensates for Master Clock Oscillator accuracy • Detects frequency of both reference clocks and synchronizes to any combination of 8 kHz, 1.544 MHz, 2.048 MHz and 19.44 MHz reference frequencies. • Allows Hardware or Microprocessor control • Pin compatible with MT90401 device. Applications • Synchronization for SDH and SONET Network Elements • Clock generation for ST-BUS and GCI backplanes Description The ZL30402 is a Network Element Phase-Locked Loop designed to synchronize SDH and SONET systems. In addition, it generates multiple clocks for legacy PDH equipment and provides timing for ST-BUS and GCI backplanes. The ZL30402 operates in NORMAL (LOCKED), HOLDOVER and FREE-RUN modes to ensure that in the presence of jitter, wander and interruptions to the reference signals, the generated clocks meet international standards. The filtering characteristics of the PLL are hardware or software selectable and they do not require any external adjustable components. The ZL30402 uses an external 20 MHz Master Clock Oscillator to provide a stable timing source for the HOLDOVER operation. The ZL30402 operates from a single 3.3 V power supply and offers a 5 V tolerant microprocessor interface. May 2006 Ordering Information ZL30402/QCC 80 Pin LQFP Trays ZL30402QCG1 80 Pin LQFP* Trays, Bake & Drypack *Pb Free Matte Tin -40 °C to +85°C ZL30402 SONET/SDH Network Element PLL Data Sheet Figure 1 - Functional Block Diagram Control State Machine MUX Microport Primary Acquisition PLL MS1 MS2 HW RESET SEC Trst C19o C34/C44 C16o C8o C4o C2o C1.5o F16o F8o PRI C6o HOLDOVER LOCK D0-D7 R/W CS C155P/N E3DS3/OC3 F0o Secondary Acquisition PLL RefAlign DS E3/DS3 JTAG IEEE 1149.1a Master Clock Frequency Calibration APLL A0-A6 Tms Tdo Tdi Tclk Clock Synthesizer Core PLL RefSel FCS C20i VDD GND |
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