Dual Driver/Comparator/Load

with Internal DACs

_______________________________________________________________________________________

9

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

SERIAL PORT TIMING (Note 28)

SCLK Frequency

50

MHz

SCLK Pulse-Width High

8ns

SCLK Pulse-Width Low

8ns

CS Low to SCLK High Setup

3.5

ns

SCLK High to CS Low Hold

3.5

ns

CS High to SCLK High Setup

3.5

ns

SCLK High to CS High Hold

3.5

ns

DIN to SCLK High Setup

3.5

ns

DIN to SCLK High Hold

3.5

ns

CS High Pulse Width

20

ns

LOAD Low Pulse Width

20

ns

RST Low Pulse Width

20

ns

CS High to LOAD Low Hold Time

20

ns

COMMON FUNCTIONS

Operating Voltage Range

(Note 29)

-1.5

+6.5

V

±2

±5

DUT_ High-Impedance Leakage

±5

µA

-10

+10

-10

+10

DUT_ Low-Leakage Mode

Leakage

-10

+10

nA

Driver in terminate mode

2

DUT_ Combined Capacitance

Driver in high impedance

4

pF

POWER SUPPLY

Positive Supply Voltage

9.5

9.75

10.5

V

Negative Supply Voltage

-5.2

-4.75

-4.5

V

Logic Supply Voltage

2.7

3.3

5.0

V

Positive Supply Current

(Note 30)

70

85

mA

Negative Supply Current

(Note 30)

150

180

mA

Logic Supply Current

(Note 30)

1.2

2

mA

Power Dissipation

(Notes 30, 31)

1.4

1.7

W

Power Dissipation per Channel

(Notes 30, 31)

700

mW

ELECTRICAL CHARACTERISTICS (continued)

Note 1:

All minimum and maximum specifications are 100% production tested, unless otherwise noted. All other test limits are

with accuracy of ±15°C.

Note 2:

Guaranteed by design and characterization.