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SST34HF164C-70-4C-LBK Datasheet(PDF) 5 Page - Silicon Storage Technology, Inc |
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SST34HF164C-70-4C-LBK Datasheet(HTML) 5 Page - Silicon Storage Technology, Inc |
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5 / 26 page  Preliminary Specifications 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C 5 ©2004 Silicon Storage Technology, Inc. S71269-01-000 9/04 SRAM Operation With BES# low and BEF# high, the SST34HF162C/164C operate as either 128K x16 or 256K x16 CMOS SRAM, with fully static operation requiring no external clocks or tim- ing strobes. The SST34HF162C/164C SRAM is mapped into the first 128 KWord address space. When BES# and BEF# are high, all memory banks are deselected and the device enters standby. Read and Write cycle times are equal. The control signals UBS# and LBS# provide access to the upper data byte and lower data byte. See Table 4 for SRAM Read and Write data byte control modes of opera- tion. SRAM Read The SRAM Read operation of the SST34HF162C/164C is controlled by OE# and BES#, both have to be low with WE# high for the system to obtain data from the outputs. BES# is used for SRAM bank selection. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. Refer to the Read cycle timing diagram, Figure 3, for further details. SRAM Write The SRAM Write operation of the SST34HF162C/164C is controlled by WE# and BES#, both have to be low for the system to write to the SRAM. During the Word-Write oper- ation, the addresses and data are referenced to the rising edge of either BES# or WE# whichever occurs first. The write time is measured from the last falling edge of BES# or WE# to the first rising edge of BES# or WE#. Refer to the Write cycle timing diagrams, Figures 4 and 5, for further details. 1269 B1.1 SuperFlash Memory (Bank 1) I/O Buffers SuperFlash Memory (Bank 2) 2/4 Mbit SRAM AMSF 1- A0 AMSS 2- A0 DQ15 - DQ0 Control Logic BEF# LBS# UBS# WE# OE# BES# Address Buffers Address Buffers Notes: 1. AMSF = Most significant flash address AMSF = A19 for SST34HF162C/164C 2. AMSS = Most significant SRAM address AMSS = A16 for SST34HF162C and A17 for SST34HF164C FUNCTIONAL BLOCK DIAGRAM |
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