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SST32HF324C-70-4C-LBK Datasheet(PDF) 6 Page - Silicon Storage Technology, Inc |
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SST32HF324C-70-4C-LBK Datasheet(HTML) 6 Page - Silicon Storage Technology, Inc |
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6 / 28 page  6 Preliminary Specifications Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C ©2005 Silicon Storage Technology, Inc. S71267-02-000 9/05 FIGURE 1: PIN ASSIGNMENTS FOR 48-BALL LBGA (10MM X 12MM) TABLE 3: PIN DESCRIPTION Symbol Pin Name Functions AMS1-A0 1. AMS=Most significant address Address Inputs To provide flash addresses: A20-A0 SRAM addresses: A17-A0 DQ15-DQ0 Data Input/output To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a flash Erase/Program cycle. The outputs are in tri-state when OE# or BES# and BEF# are high. BES# SRAM Memory Bank Enable To activate the SRAM memory bank when BES# is low. BEF# Flash Memory Bank Enable To activate the flash memory bank when BEF# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the Write operations. VDDF Power Supply (Flash) 2.7-3.3V Power Supply to flash only. VDDS Power Supply (SRAM) 2.7-3.3V Power Supply to SRAM only VSS Ground UBS# Upper Byte Control (SRAM) To enable DQ15-DQ8 LBS# Lower Byte Control (SRAM) To enable DQ7-DQ0 NC No Connection Unconnected Pins T3.0 1267 BES# A10 OE# A11 A13 WE# VSS DQ5 DQ7 A8 A17 VDDS DQ1 DQ2 DQ4 A5 UBS# A16 A1 A0 DQ0 DQ8 BEF# VSS A2 A3 A6 DQ3 DQ10 DQ9 A4 A7 A18 DQ12 VDDF DQ11 A19 A20 NC A12 DQ6 DQ13 A9 A14 A15 LBS# DQ15 DQ14 A B C D E F G H SST32HF324C 6 5 4 3 2 1 TOP VIEW (balls facing down) |
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