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PGA2500 Datasheet(PDF) 3 Page - Burr-Brown (TI) |
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PGA2500 Datasheet(HTML) 3 Page - Burr-Brown (TI) |
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3 / 17 page  PGA2500 SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003 www.ti.com 3 ELECTRICAL CHARACTERISTICS All parameters specified with TA = +25 °C, VA+ = +5V, VA− = −5V, VD− = −5V, and V COMIN = 0V, unless otherwise noted. PARAMETER TEST CONDITIONS PGA2500 UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC Characteristics Step Size Gain = 10dB through 65dB 1 dB Gain Error All Gain Settings 0.5 dB AC Characteristics THD+N with fIN = 1kHz Gain = 0dB, VOUT = 3.5VRMS, VCOMIN = 0V Gain = 30dB, VOUT = 3.5VRMS, VCOMIN = 0V −114 −108 −108 −102 dB dB Analog Input Maximum Input Voltage Gain = 0dB VA− +1.5 VA+ −2.0 V Input Resistance Per Input Pin Differential 4600 9200 Ω Ω Analog Output Output Voltage Range VCOMIN = 0V, RL = 600 Ω VA− +0.9 VA+ −0.9 V Output Offset Voltage DC Servo On, Any Gain ±0.04 ±1 mV Input Referred Offset DC Servo Off, Gain = 30dB ±1 mV Output Resistive Loading 600 Ω Load Capacitance Stability 100 pF Short Circuit Current 10-second duration 100 mA Digital Characteristics High-Level Input Voltage, VIH +2.0 VA+ V Low-Level Input Voltage, VIL −0.3 0.8 V High-Level Output Voltage, VOH IO = 200 µA (VA+) − 1.0 V Low-Level Output Voltage, VOL IO = −3.2mA 0.4 V Input Leakage Current, IIN 2 10 µA Switching Characteristics Serial Clock (SCLK) Frequency fSCLK 0 6.25 MHz Serial Clock (SCLK) Pulse Width Low tPH 80 ns Serial Clock (SCLK) Pulse Width High tPL 80 ns Input Timing SDI Setup Time tSDS 20 ns SDI Hold Time tSDH 20 ns CS Falling to SCLK Rising tCSCR 90 ns SCLK Falling to CS Rising tCFCS 35 ns Output Timing CS Low to SDO Active tCSO 35 ns SCLK Falling to SDO Data Valid tCFDO 60 ns CS High to SDO High Impedance tCSZ 100 ns Power Supply Operating Voltage VA+ +4.75 +5 +5.25 V VA− −4.75 −5 −5.25 V VD− −4.75 −5 −5.25 V Quiescent Current IA+ VA+ = +5V 30 40 mA IA− VA− = −5V 30 40 mA ID− VD− = −5V 1 2 mA |
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