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ZL30122GGG Datasheet(PDF) 11 Page - Zarlink Semiconductor Inc

Part # ZL30122GGG
Description  SONET/SDH Low Jitter Line Card Synchronizer
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Manufacturer  ZARLINK [Zarlink Semiconductor Inc]
Direct Link  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

ZL30122GGG Datasheet(HTML) 11 Page - Zarlink Semiconductor Inc

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ZL30122
Data Sheet
11
Zarlink Semiconductor Inc.
1.3
Ref and Sync Inputs
There are three reference clock inputs (ref0 to ref2) available to the DPLL. Reference selection can be controlled
using a built-in state machine or set in a manual mode.The selected reference input is used to synchronize the
output clocks.
Figure 3 - Reference and Sync Inputs
In addition to the reference inputs, the DPLL has three optional frame pulse synchronization inputs (sync0 to
sync2) used to align the output frame pulses. The syncn input is selected with its corresponding refn input, where n
= 0, 1, or 2. Note that the sync input cannot be used to synchronize the DPLL, it only determines the alignment of
the frame pulse outputs. An example of output frame pulse alignment is shown in Figure 4.
Figure 4 - Output Frame Pulse Alignment
ref2:0
sync2:0
DPLL
refn
diff_clk/sdh_clk/p_clk
sdh/p_fp
Without a frame pulse
signal at the sync input,
the output frame pulses
will align to any arbitrary
cycle of its associated
output clock.
syncn - no frame pulse signal present
When a frame pulse
signal is present at the
sync input, the DPLL
will align the output
frame pulses to the
output clock edge that is
aligned to the input
frame pulse.
refn
syncn
n = 0, 1, 2
n = 0, 1, 2
diff_clk/sdh_clk/p_clk
sdh_fp/p_fp


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