ZL30108

Data Sheet

7

Zarlink Semiconductor Inc.

21

C19o

Clock 19.44 MHz (Output). This CMOS output is used in SONET/SDH applications.

This clock output pad includes a Schmitt input which serves as a PLL feedback path;

proper transmission-line termination should be applied to maintain reflections below

Schmitt trigger levels.

22

AGND

Analog Ground. 0V

23

24

F8ko

Frame Pulse (Output). This is an CMOS 8 kHz active high 31 ns framing pulse, which

marks the beginning of a 125

µs frame.

This clock output pad includes a Schmitt input which serves as a PLL feedback path;

proper transmission-line termination should be applied to maintain reflections below

Schmitt trigger levels.

25

AGND

Analog Ground. 0V

26

REF_SEL

Reference Select 0 (Input/Output). As an input REF_SEL selects the reference input

that is used for synchronization; See Table 4.

0: REF0

1: REF1

This pin is internally pulled down to GND.

27

REF0

Reference (Input). This is one of two (REF0 and REF1) input reference sources used for

synchronization. One of seven possible frequencies may be used: 2 kHz, 8 kHz,

1.544 MHz, 2.048 MHz, 8.192 MHz,16.384 MHz or 19.44 MHz. This pin is internally

pulled down to GND.

28

REF1

Reference (Input). See REF0 pin description.

29

OOR_SEL

Out Of Range Selection (Input). This input selects the frequency acceptance limits of

the reference monitor: See Table 2.

0: 40 - 52 ppm

1: 64 - 83 ppm

30

IC

Internal Connection. Connect this pin to GND.

31

32

TIE_CLR

TIE Circuit Reset (Input). A logic low at this input resets the Time Interval Error (TIE)

correction circuit resulting in a realignment of input phase with output phase.

33

IC

Internal Connection. Package E-pad, this pin is internally connected to device GND, it

can be left unconnected or it can be connected to GND.

Pin #

Name

Description