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ZL30106QDG Datasheet(PDF) 2 Page - Zarlink Semiconductor Inc |
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ZL30106QDG Datasheet(HTML) 2 Page - Zarlink Semiconductor Inc |
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2 / 48 page  ZL30106 Data Sheet 2 Zarlink Semiconductor Inc. Description The ZL30106 SONET/SDH/PDH network interface Digital Phase-Locked Loop (DPLL) provides timing and synchronization for SONET/SDH and PDH network interface cards. The ZL30106 generates SONET/SDH, PDH, ST-BUS and other TDM clock and framing signals that are phase locked to one of three network references. It helps ensure system reliability by monitoring its references for frequency accuracy and stability and by maintaining tight phase alignment between the input reference clock and clock outputs. The ZL30106 output clocks wander and jitter generation are compliant with the associated transport medium specifications. |
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