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SN74LVC540ADGVR Datasheet(PDF) 2 Page - Texas Instruments |
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SN74LVC540ADGVR Datasheet(HTML) 2 Page - Texas Instruments |
2 / 17 page www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) OE1 OE2 To Seven Other Channels A1 Y1 1 19 2 18 SN54LVC540A, SN74LVC540A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCAS297M – JANUARY 1993 – REVISED MAY 2005 The 3-state control gate is a 2-input AND gate with active-low inputs so that, if either output-enable (OE1 or OE2) input is high, all outputs are in the high-impedance state. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE INPUTS OUTPUT Y OE1 OE2 A L L L H L L H L H X X Z X H X Z LOGIC DIAGRAM (POSITIVE LOGIC) 2 |
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