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DS90CR284 Datasheet(PDF) 4 Page - National Semiconductor (TI) |
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DS90CR284 Datasheet(HTML) 4 Page - National Semiconductor (TI) |
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4 / 13 page  Electrical Characteristics (Continued) Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Conditions Min Typ Max Units RECEIVER SUPPLY CURRENT I CCRW Receiver Supply Current, Worst Case C L = 8 pF, f = 32.5 MHz 64 77 mA Worst Case Pattern f = 37.5 MHz 70 85 mA ( Figures 1, 3) f = 66 MHz 110 140 mA I CCRZ Receiver Supply Current, Power Down = Low Power Down Receiver Outputs in Previous State during Power Down Mode 1 10 µA Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation. Note 2: Typical values are given for VCC = 5.0V and TA = +25˚C. Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except VOD and ∆V OD). Note 4: ESD Rating: HBM (1.5 k Ω, 100 pF) PLL VCC ≥ 1000V All other pins ≥ 2000V EIAJ (0 Ω, 200 pF) ≥ 150V Note 5: VOS previously referred as VCM. Transmitter Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Min Typ Max Units LLHT LVDS Low-to-High Transition Time ( Figure 2) 0.75 1.5 ns LHLT LVDS High-to-Low Transition Time ( Figure 2) 0.75 1.5 ns TCIT TxCLK IN Transition Time ( Figure 4)8 ns TCCS TxOUT Channel-to-Channel Skew (Note 6) ( Figure 5) 350 ps TPPos0 Transmitter Output Pulse Position for Bit 0 f = 66 MHz −0.30 0 0.30 ns ( Figure 16) TPPos1 Transmitter Output Pulse Position for Bit 1 1.70 (1/7)T clk 2.50 ns TPPos2 Transmitter Output Pulse Position for Bit 2 3.60 (2/7)T clk 4.50 ns TPPos3 Transmitter Output Pulse Position for Bit 3 5.90 (3/7)T clk 6.75 ns TPPos4 Transmitter Output Pulse Position for Bit 4 8.30 (4/7)T clk 9.00 ns TPPos5 Transmitter Output Pulse Position for Bit 5 10.40 (5/7)T clk 11.10 ns TPPos6 Transmitter Output Pulse Position for Bit 6 12.70 (6/7)T clk 13.40 TCIP TxCLK IN Period ( Figure 6) 15 T 50 ns TCIH TxCLK IN High Time ( Figure 6) 0.35T 0.5T 0.65T ns TCIL TxCLK IN Low Time ( Figure 6) 0.35T 0.5T 0.65T ns TSTC TxIN Setup to TxCLK IN ( Figure 6) 5 3.5 ns THTC TxIN Hold to TxCLK IN ( Figure 6) 2.5 1.5 ns TCCD TxCLK IN to TxCLK OUT Delay @ 25˚C, 3.5 8.5 ns V CC = 5.0V (Figure 8) TPLLS Transmitter Phase Lock Loop Set ( Figure 10)10 ms TPDD Transmitter Power Down Delay ( Figure 14) 100 ns Note 6: This limit based on bench characterization. www.national.com 4 |
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