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Theory of Operation

FIGURE 1.

Trigger Operation

As shown in Figure 1 and the logic diagram, before an

input trigger occurs, the one shot is in the quiescent state

valid trigger is recognized, which turns on comparator C1

and Nchannel transistor N11. At the same time the output

point the output of comparator C1 changes state and tran-

sistor N1 turns off. Comparator C1 then turns off while at

the same time comparator C2 turns on. With transistor N1

output latch to reset (Q goes LOW) while at the same time

disabling comparator C2. This ends the timing cycle with

the monostable in the quiescent state, waiting for the next

trigger.

A valid trigger is also recognized when trigger input B goes

to be zero. Both comparators are “off” with the total device

current due only to reverse junction leakages. An added

feature of the MM74HC123A is that the output latch is set

via the input trigger without regard to the capacitor voltage.

Thus, propagation delay from trigger to Q is independent of

waveform.

Retrigger Operation

The MM74HC123A is retriggered if a valid trigger occurs 3

followed by another trigger 4 before the Q output has

returned to the quiescent (zero) state. Any retrigger, after

increase in output pulse width T. When a valid retrigger is

after the last valid retrigger.

Because the trigger-control circuit flip-flop resets shortly

function of internal propagation delays and the discharge

Another removal/retrigger time occurs when a short clear

pulse is used. Upon receipt of a clear, the one shot must

charge the capacitor up to the upper trip point before the

one shot is ready to receive the next trigger. This time is

dependent on the capacitor used and is approximately: