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MM74HC123AN Datasheet(PDF) 5 Page - Fairchild Semiconductor |
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MM74HC123AN Datasheet(HTML) 5 Page - Fairchild Semiconductor |
5 / 10 page 5 www.fairchildsemi.com Theory of Operation FIGURE 1. Trigger Operation As shown in Figure 1 and the logic diagram, before an input trigger occurs, the one shot is in the quiescent state with the Q output LOW, and the timing capacitor CEXT com- pletely charged to VCC. When the trigger input A goes from VCC to GND (while inputs B and clear are held to VCC) a valid trigger is recognized, which turns on comparator C1 and Nchannel transistor N11. At the same time the output latch is set. With transistor N1 on, the capacitor CEXT rap- idly discharges toward GND until VREF1 is reached. At this point the output of comparator C1 changes state and tran- sistor N1 turns off. Comparator C1 then turns off while at the same time comparator C2 turns on. With transistor N1 off, the capacitor CEXT begins to charge through the timing resistor, REXT, toward VCC. When the voltage across CEXT equals VREF2, comparator C2 changes state causing the output latch to reset (Q goes LOW) while at the same time disabling comparator C2. This ends the timing cycle with the monostable in the quiescent state, waiting for the next trigger. A valid trigger is also recognized when trigger input B goes from GND to VCC (while input A is at GND and input clear is at VCC2). The MM74HC123A can also be triggered when clear goes from GND to VCC (while A is at GND and B is at VCC6). It should be noted that in the quiescent state CEXT is fully charged to VCC causing the current through resistor REXT to be zero. Both comparators are “off” with the total device current due only to reverse junction leakages. An added feature of the MM74HC123A is that the output latch is set via the input trigger without regard to the capacitor voltage. Thus, propagation delay from trigger to Q is independent of the value of CEXT, REXT, or the duty cycle of the input waveform. Retrigger Operation The MM74HC123A is retriggered if a valid trigger occurs 3 followed by another trigger 4 before the Q output has returned to the quiescent (zero) state. Any retrigger, after the timing node voltage at the R/CEXT pin has begun to rise from VREF1, but has not yet reached VREF2, will cause an increase in output pulse width T. When a valid retrigger is initiated 4, the voltage at the R/CEXT pin will again drop to VREF1 before progressing along the RC charging curve toward VCC. The Q output will remain HIGH until time T, after the last valid retrigger. Because the trigger-control circuit flip-flop resets shortly after CX has discharged to the reference voltage of the lower reference circuit, the minimum retrigger time, trr is a function of internal propagation delays and the discharge time of CX: Another removal/retrigger time occurs when a short clear pulse is used. Upon receipt of a clear, the one shot must charge the capacitor up to the upper trip point before the one shot is ready to receive the next trigger. This time is dependent on the capacitor used and is approximately: |
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