MC9328MX21VK datasheet(8/98 Pages) FREESCALE

Part #	MC9328MX21VK

Description	i.MX family of microprocessors

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Manufacturer	FREESCALE [Freescale Semiconductor, Inc]

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MC9328MX21 Technical Data, Rev. 3.1

8

Freescale Semiconductor

Signal Descriptions

PS

Control signal output for source driver (Sharp panel dedicated signal). This signal is multiplexed with the

SLCDC1_CS.

CLS

Start signal output for gate driver. This signal is invert version of PS (Sharp panel dedicated signal). This

signal is multiplexed with the SLCDC1_RS.

REV

Signal for common electrode driving signal preparation (Sharp panel dedicated signal). This signal is

multiplexed with SLCDC1_D0.

Smart LCD Controller

SLCDC1_CLK

SLCDC Clock output signal. This signal is multiplexed and available at 2 alternate locations. These are

SPL_SPR and SD2_CLK signals of LCDC and SD2, respectively.

SLCDC1_CS

SLCDC Chip Select output signal. This signal is multiplexed and available at 2 alternate signal locations.

These are PS and SD2_CMD signals of LCDC and SD2, respectively.

SLCDC1_RS

SLCDC Register Select output signal. This signal is multiplexed and available at 2 alternate signal

locations. These are CLS and SD2_D3 signals of LCDC and SD2, respectively.

SLCDC1_D0

SLCDC serial data output signal. This signal is multiplexed and available at 2 alternate signal locations.

These are and REV and SD2_D2 signals of LCDC and SD2, respectively. This signal is inactive when a

parallel data interface is used.

SLCDC1_DAT[15:0]

SLCDC Data output signals for connection to a parallel SLCD panel interface. These signals are

multiplexed with LD[15:0] while an alternate 8-bit SLCD muxing is available on LD[15:8]. Further

alternate muxing of these signals are available on some of the USB OTG and USBH1 signals.

SLCDC2_CLK

SLCDC Clock input signal for pass through to SLCD device. This signal is multiplexed with SSI3_CLK

signal from SSI3.

SLCDC2_CS

SLCDC Chip Select input signal for pass through to SLCD device. This signal is multiplexed with

SSI3_TXD signal from SSI3.

SLCDC2_RS

SLCDC Register Select input signal for pass through to SLCD device. This signal is multiplexed with

SSI3_RXD signal from SSI3.

SLCDC2_D0

SLCD Data input signal for pass through to SLCD device. This signal is multiplexed with SSI3_FS signal

from SSI3.

Bus Master Interface (BMI)

BMI_D[15:0]

BMI bidirectional data bus. Bus width is programmable between 8-bit or 16-bit.These signals are

multiplexed with LD[15:0] and SLCDC_DAT[15:0].

BMI_CLK_CS

BMI bidirectional clock or chip select signal.This signal is multiplexed with LSCLK of LCDC.

BMI_WRITE

BMI bidirectional signal to indicate read or write access. This is an input signal when the BMI is a slave

and an output signal when BMI is the master of the interface. BMI_WRITE is asserted for write and

negated for read.This signal is muxed with LD[17] of LCDC.

BMI_READ

BMI output signal to enable data read from external slave device. This signal is not used and driven high

when BMI is slave.This signal is multiplexed with CONTRAST signal of LCDC.

BMI_READ_REQ

BMI Read request output signal to external bus master. This signal is active when the data in the TXFIFO

is larger or equal to the data transfer size of a single external BMI access.This signal is muxed with

LD[16] of LCDC.

BMI_RXF_FULL

BMI Receive FIFO full active high output signal to reflect if the RxFIFO reaches water mark value.This

signal is muxed with VSYNC of the LCDC.

BMI_WAIT

BMI Wait—Active low signal to wait for data ready (read cycle) or accepted (write_cycle). Also

multiplexed with VSYNC.

Table 2. i.MX21 Signal Descriptions (Continued)

Signal Name

Function/Notes

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