CC1000-RTR1 datasheet(6/55 Pages) TI

Part #	CC1000-RTR1

Description	Single Chip Very Low Power RF Transceiver

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Manufacturer	TI [Texas Instruments]

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6 / 55 page

CC1000

SWRS048A

Page 6 of 55

Parameter

Min.

Typ.

Max.

Unit

Condition / Note

Frequency Synthesiser

Section

Crystal Oscillator Frequency

3

16

MHz

Crystal frequency can be 3-4, 6-8

or 9-16 MHz. Recommended

frequencies are 3.6864, 7.3728,

11.0592 and 14.7456. See page

35 for details.

Crystal frequency accuracy

requirement

± 50

± 25

ppm

433 MHz

868 MHz

The crystal frequency accuracy

and drift (ageing and

temperature dependency) will

determine the frequency accuracy

of the transmitted signal.

Crystal operation

Parallel

C171 and C181 are loading

capacitors, see page 35

Crystal load capacitance

12

22

16

30

16

pF

3-4 MHz, 22 pF recommended

6-8 MHz, 16 pF recommended

9-16 MHz, 16 pF recommended

Crystal oscillator start-up time

5

1.5

2

ms

3.6864 MHz, 16 pF load

7.3728 MHz, 16 pF load

16 MHz, 16 pF load

Output signal phase noise

-85

dBc/Hz

At 100 kHz offset from carrier

PLL lock time (RX / TX turn time)

200

µs

Up to 1 MHz frequency step

PLL turn-on time, crystal oscillator

on in power down mode

250

µs

Crystal oscillator running

Digital Inputs/Outputs

Logic “0” input voltage

0

0.3*VDD

V

Logic ”1” input voltage

0.7*VDD

VDD

V

Logic “0” output voltage

0

0.4

V

Output current -2.5 mA,

3.0 V supply voltage

Logic “1” output voltage

2.5

VDD

V

Output current 2.5 mA,

3.0 V supply voltage

Logic “0” input current

NA

-1

µA

Input signal equals GND

Logic “1” input current

NA

1

µA

Input signal equals VDD

DIO setup time

20

ns

TX mode, minimum time DIO

must be ready before the positive

edge of DCLK

DIO hold time

10

ns

TX mode, minimum time DIO

must be held after the positive

edge of DCLK

Serial interface (PCLK, PDATA and

PALE) timing specification

See Table 2 page 14

Current Consumption

Power Down mode

0.2

1

µA

Oscillator core off

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