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MB89498 Datasheet(PDF) 2 Page - Fujitsu Component Limited. |
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MB89498 Datasheet(HTML) 2 Page - Fujitsu Component Limited. |
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2 / 57 page  MB89490 Series 2 (Continued) • High speed operating capability at low voltage • Minimum execution time : 0.32 µs/12.5 MHz •F2MC-8L family CPU core • PLL circuit for sub-clock • Embedded for PLL clock multiplication circuit for sub-clock • Operating clock (PLL for sub-clock) can be selected from no multiplication or 4 times of the sub-clock oscillation frequency. •6 timers PWM timer × 2 8/16-bit timer/counter × 2 21-bit timebase timer Watch prescaler • External interrupt Edge detection (selectable edge) : 8 channels Low level interrupt (wake-up function) : 8 channels • 10-bit A/D converter (8 channels) 10-bit successive approximation type • UART/SIO Synchronous/asynchronous data transfer capability •SIO Switching of synchronous data transfer capability • LCD controller/driver Max 32 segments output × 4 commons •I2C interface circuit • Remote receiver circuit • Low-power consumption mode Stop mode (oscillation stops so as to minimize the current consumption.) Sleep mode (CPU stops so as to reduce the current consumption to approx. 1/3 of normal.) Watch mode (operation except the watch prescaler stops so as to reduce the power comsumption to an extremely low level.) Sub-clock mode • Watchdog timer reset • I/O ports : Max 66 channels Instruction set optimized for controllers Multiplication and division instructions 16-bit arithmetic operations Branch instructions by test bit Bit manipulation instructions, etc. |
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