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M27W801-200F6TR Datasheet(PDF) 9 Page - STMicroelectronics |
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M27W801-200F6TR Datasheet(HTML) 9 Page - STMicroelectronics |
9 / 24 page M27W801 Device operation 9/24 2.4 System considerations The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of E. The magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device at the output. The associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling capacitors. It is recommended that a 0.1µF ceramic capacitor be used on every device between VCC and VSS. This should be a high frequency capacitor of low inherent inductance and should be placed as close to the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be used between VCC and VSS for every eight devices. The bulk capacitor should be located near the power supply connection point. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces. 2.5 Programming The M27W801 has been designed to be fully compatible with the M27C801 and has the same electronic signature. As a result the M27W801 can be programmed as the M27C801 on the same programming equipment applying 12.75V on VPP and 6.25V on VCC by the use of the same PRESTO IIB algorithm. When delivered (and after each ‘1’s erasure for UV EPROM), all bits of the M27W801 are in the "1" state. Data is introduced by selectively programming "0"s into the desired bit locations.Although only '0' will be programmed, both "1" and "0" can be present in the data word. The only way to change a ‘0’ to a ‘1’ is by die exposure to ultraviolet light (UV EPROM). The M27W801 is in the programming mode when VPP input is at 12.75V and E is pulsed to VIL. The data to be programmed is applied to 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. VCC is specified to be 6.25V ± 0.25V. 2.6 PRESTO IIB programming algorithm PRESTO IIB Programming Algorithm allows the whole array to be programmed with a guaranteed margin, in a typical time of 52.5 seconds. This can be achieved with STMicroelectronics M27W801 due to several design innovations to improve programming efficiency and to provide adequate margin for reliability. Before starting the programming the internal MARGIN MODE circuit must be set in order to guarantee that each cell is programmed with enough margin. Then a sequence of 50µs program pulses are applied to each byte until a correct verify occurs (see Figure 5). No overprogram pulses are applied since the verify in MARGIN MODE at VCC much higher than 3.6V, provides the necessary margin. |
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