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M37515M4-XXXHP Datasheet(PDF) 27 Page - Mitsubishi Electric Semiconductor |
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M37515M4-XXXHP Datasheet(HTML) 27 Page - Mitsubishi Electric Semiconductor |
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27 / 54 page  27 M37515M4-XXXHP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS START/STOP condition control register Oscillation frequency f(XIN) (MHz) Fig. 30 Address data communication format Fig. 29 Structure of I2C START/STOP condition control register Note: Do not set an odd number to the START/STOP condition set bit (SSC4 to SSC0). Table 9 Recommended set value to START/STOP condition set bits (SSC4–SSC0) for each oscillation frequency Main clock divide ratio System clock φ (MHz) SCL release time ( µs) Setup time ( µs) Hold time ( µs) 8 8 4 2 2 8 2 2 XXX11010 XXX11000 XXX00100 XXX01100 XXX01010 XXX00100 3.375 µs (13.5 cycles) 3.125 µs (12.5 cycles) 2.5 µs (2.5 cycles) 3.25 µs (6.5 cycles) 2.75 µs (5.5 cycles) 2.5 µs (2.5 cycles) 6.75 µs (27 cycles) 6.25 µs (25 cycles) 5.0 µs (5 cycles) 6.5 µs (13 cycles) 5.5 µs (11 cycles) 5.0 µs (5 cycles) 3.375 µs (13.5 cycles) 3.125 µs (12.5 cycles) 2.5 µs (2.5 cycles) 3.25 µs (6.5 cycles) 2.75 µs (5.5 cycles) 2.5 µs (2.5 cycles) 4 1 2 1 b7 b0 I2C START/STOP condition control register START/STOP condition set bit SCL/SDA interrupt pin polarity selection bit 0 : Falling edge active 1 : Rising edge active SCL/SDA interrupt pin selection bit 0 : SDA valid 1 : SCL valid Reserved Do not write “1” to this bit. SIS SIP SSC4 SSC3 SSC2 SSC1 SSC0 (S2D : address 003016) S Slave address R/W A Data A/A P A Data 7 bits “0” 1 to 8 bits 1 to 8 bits (1) A master-transmitter transnmits data to a slave-receiver S Slave address R/W A Data A P A Data 7 bits “1” 1 to 8 bits 1 to 8 bits (2) A master-receiver receives data from a slave-transmitter 7 bits “0” 8 bits (3) A master-transmitter transmits data to a slave-receiver with a 10-bit address 1 to 8 bits 1 to 8 bits S R/W A Slave address 1st 7 bits Slave address 2nd bytes A A Data Data P A/A 7 bits “0” 8 bits (4) A master-receiver receives data from a slave-transmitter with a 10-bit address S : START condition A : ACK bit Sr : Restart condition P : STOP condition R/W : Read/Write bit 7 bits “1” 1 to 8 bits 1 to 8 bits S R/W A Slave address 1st 7 bits Slave address 2nd bytes A Sr Slave address 1st 7 bits R/W A Data Data P A : Master to slave : Slave to master A |
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