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MB90F351ESPMC Datasheet(PDF) 9 Page - Fujitsu Component Limited.

Part # MB90F351ESPMC
Description  16-bit Proprietary Microcontrollers
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Manufacturer  FUJITSU [Fujitsu Component Limited.]
Direct Link  http://edevice.fujitsu.com/fmd/en/index.html
Logo FUJITSU - Fujitsu Component Limited.

MB90F351ESPMC Datasheet(HTML) 9 Page - Fujitsu Component Limited.

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MB90350E Series
9
■ PRODUCT LINEUP 2 (With Clock supervisor function)
• Flash memory products
(Continued)
Part Number
Parameter
MB90F356E,
MB90F357E
MB90F356TE,
MB90F357TE
MB90F356ES,
MB90F357ES
MB90F356TES,
MB90F357TES
Type
Flash memory products
CPU
F2MC-16LX CPU
System clock
On-chip PLL clock multiplier (
×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL
× 6)
ROM
Dual operation flash memory
64 Kbytes : MB90F356E(S), MB90F356TE(S)
128 Kbytes : MB90F357E(S), MB90F357TE(S)
RAM
4 Kbytes
Emulator-specific
power supply*1
Sub clock pin
(X0A, X1A)
Yes
No
(internal CR oscillation can be used as
sub clock)
Clock supervisor
Yes
Low voltage/CPU
operation detection
reset
No
Yes
No
Yes
Operating
voltage range
3.5 V to 5.5 V : at normal operating (not using A/D converter)
3.5 V to 5.5 V : at using A/D converter/Flash programming
3.5 V to 5.5 V : at using external bus
Operating
temperature range
−40 °C to +125 °C
Package
LQFP-64
UART
2 channels
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
I2C (400 kbps)
1 channel
A/D Converter
15 channels
10-bit or 8-bit resolution
Conversion time : Min 3
µs includes sample time (per one channel)
16-bit Reload Timer
(4 channels)
Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys
= Machine clock frequency)
Supports External Event Count function.
16-bit I/O Timer
(2 channels)
I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1.
I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7.
Signals an interrupt when overflowing.
Supports Timer Clear when a match with Output Compare (Channel 0, 4) .
Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys
= Machine clock frequency)
16-bit Output
Compare
4 channels
Signals an interrupt when 16-bit I/O Timer matches with output compare registers.
A pair of compare registers can be used to generate an output signal.


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