MT9160B/61B

Advance Information

84

Motorola/National operation. Refer to the relative

timing diagrams of Figures 5 and 6.

Receive data is sampled on the rising edge of SCLK

while transmit data is made available concurrent with

the falling edge of SCLK.

Flexible Digital Interface

A serial link is required to transport data between the

MT9160B/61B and an external digital transmission

device. The MT9160B/61B utilizes the ST-BUS

architecture defined by Zarlink Semiconductor but

Figure 4 - Serial Port Relative Timing for Intel Mode 0

Figure 5 - Serial Port Relative Timing for Motorola Mode 00/National Microwire

XX

R/W

➀

Delays due to internal processor timing which are transparent.

y

The MT9160:-latches received data on the rising edge of SCLK.

➂

The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The

➃

A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.

➄

The COMMAND/ADDRESS byte contains:

➀

➂

➃

➄

➀

y

➂

➃

COMMAND/ADDRESS

DATA INPUT/OUTPUT

COMMAND/ADDRESS:

DATA 1

RECEIVE

DATA 1

TRANSMIT

SCLK

CS

-outputs transmit data on the falling edge of SCLK.

subsequent byte is always data until terminated via CS returning high.

1 bit - Read/Write

3 bits - Addressing Data

4 bits - Unused

XX

➀

➂

➃

➀

y

➂

➃

COMMAND/ADDRESS

DATA INPUT/OUTPUT

COMMAND/ADDRESS:

DATA 2

RECEIVE

DATA 1

TRANSMIT

SCLK

CS

R/W

X

➀

Delays due to internal processor timing which are transparent.

➂

The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The

➃

A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.

➄

The COMMAND/ADDRESS byte contains:

subsequent byte is always data until terminated via CS returning high.

1 bit - Read/Write

3 bits - Addressing Data

4 bits - Unused

➄

y

The MT9160:-latches received data on the rising edge of SCLK.

-outputs transmit data on the falling edge of SCLK.

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