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IRS21844SPBF Datasheet(PDF) 2 Page - International Rectifier

Part # IRS21844SPBF
Description  HIGH AND LOW SIDE DRIVER
Download  23 Pages
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Manufacturer  IRF [International Rectifier]
Direct Link  http://www.irf.com
Logo IRF - International Rectifier

IRS21844SPBF Datasheet(HTML) 2 Page - International Rectifier

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IRS2181/IRS21814(S)PbF
www.irf.com
2
Symbol
Definition
Min.
Max.
Units
VB
High-side floating absolute voltage
-0.3
620
(Note 1)
VS
High-side floating supply offset voltage
VB - 20
VB + 0.3
VHO
High-side floating output voltage
VS - 0.3
VB + 0.3
VCC
Low-side and logic fixed supply voltage
-0.3
20
(Note 1)
VLO
Low-side output voltage
-0.3
VCC + 0.3
VIN
Logic input voltage (HIN & LIN)
VSS - 0.3
VCC + 0.3
VSS
Logic ground (IRS21814 only)
VCC - 20
VCC + 0.3
dVS/dt
Allowable offset supply voltage transient
50
V/ns
(8-lead PDIP)
1.0
PD
Package power dissipation @ TA ≤ +25 °C
(8-lead SOIC)
0.625
(14-lead PDIP)
1.6
(14-lead SOIC)
1.0
(8-lead PDIP)
125
RthJA
Thermal resistance, junction to ambient
(8-lead SOIC)
200
(14-lead PDIP)
75
(14-lead SOIC)
120
TJ
Junction temperature
150
TS
Storage temperature
-50
150
TL
Lead temperature (soldering, 10 seconds)
300
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
V
°C/W
W
°C
Note 2: Logic operational for VS of -5 V to +600 V. Logic state held for VS of -5 V to -VBS. (Please refer to the Design Tip
DT97-3 for more details).
VB
High-side floating supply absolute voltage
VS + 10
VS + 20
VS
High-side floating supply offset voltage
Note 2
600
VHO
High-side floating output voltage
VS
VB
VCC
Low-side and logic fixed supply voltage
10
20
VLO
Low-side output voltage
0
VCC
VIN
Logic input voltage (HIN & LIN)
VSS
VCC
VSS
Logic ground (IRS21814 only)
-5
5
TA
Ambient temperature
-40
125
°C
V
Symbol
Definition
Min.
Max.
Units
Recommended Operating Conditions
The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the
recommended conditions. The VS and VSS offset rating are tested with all supplies biased at a 15 V differential.
Note 1: All supplies are fully tested at 25 V and an internal 20 V clamp exists for each supply.


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