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VSC7139 Datasheet(PDF) 7 Page - Vitesse Semiconductor Corporation |
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VSC7139 Datasheet(HTML) 7 Page - Vitesse Semiconductor Corporation |
7 / 18 page VITESSE SEMICONDUCTOR CORPORATION Preliminary Datasheet VSC7139 Quad Transceiver for Gigabit Ethernet and Fibre Channel G52196-0, Rev 3.3 Page 7 5/14/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Figure 4: Receive Timing Waveforms Table 4: Receive AC Characteristics NOTE: (1) Probability of recovery for data acquisition is 95% per Section 5.3 of FC-PH, rev. 4.3. Parameters Description Min Typ Max Units Conditions T1 TTL Outputs Valid prior to RCx1/ RCx0 rise 4.0 3.0 TBD — — — — — — ns @ 1.0625Gb/s @ 1.25Gb/s @ 1.36Gb/s T2 TTL Outputs Valid after RCx1 or RCx0 rise 3.0 2.0 TBD — — — — — — ns @ 1.0625Gb/s @ 1.25Gb/s @ 1.36Gb/s T3 Delay between rising edge of RCx1 to rising edge of RCx0 10 x TRX -500 — 10 x TRX +500 ps TRX is the bit period of the incoming data on Rx. T4 Period of RCx1 and RCx0 1.98 x TREF — 2.02 x TREF ps Whether or not locked to serial data. TR, TF TTL Output rise and fall time —— 2.4 ns Between VIL(max) and VIH(min), into 10 pf. load. RLAT Latency from serial bit Rx0 to rising edge RCx1 12bc + 2.77ns — 13bc + 7.28ns bc = Bit clock ns = Nano second TLOCK Data acquisition lock time(1) —— 1400 bit times 8B/10B IDLE pattern. Tested on a sample basis RCx0 Rx(0:9) RCx1 SYNCx RCM=LOW RCx0 RCx1 RCM=HIGH VALID VALID VALID T1 T2 RLAT +/-Rx Rx0 Rx1 Rx2 RCx1 |
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