MITSUBISHI MEMORY CARD

STATIC RAM CARDS

MITSUBISHI

ELECTRIC

10/14

Apr. 1999 Rev. 1.2

TIMING DIAGRAM (Attribute)

Read Cycle

WE#=“H” level

REG#=“L” level

Note 5 : Test Conditions

Input pulse levels

Input pulse rise, fall time : tr=tf=10ns

Reference voltage

Input

Output

(ten and tdis are measured when output voltage is ± 500mV from steady state. )

Load

: 100pF + 1 TTL gate

5pF + 1 TTL gate (at ten and tdis measuring)

6 :

Indicates the don’t care input

7 : Writing is executed in overlap of CE# and WE# are “L” level. (only for Common Memory)

8 : Don’t apply inverted phase signal externally when Dm pin is in output mode.

9 : CE# is indicated as follows:

Read A/Write A : CE#=CE1#=CE2#

Read B/Write B : CE#=CE1#, CE2#=“H” level

Read C/Write C : CE#=CE2#, CE1#=“H” level

tcRR

t

a

ta

(CE)R

ten(CE)R

ten(OE)R

tdis(OE)R

(A)R

ta(OE)R

OUTPUT VALID

Hi-Z

An

Dm

OE#

CE#