U846B

TELEFUNKEN Semiconductors

Rev. A2, 03-Feb-97

4 (13)

Asynchronous Debouncing Times

Ditigal debouncing by clock count makes all inputs

insusceptible to short interference pulses. The switch

input stages INT, WASH, PARK are debounced at the

positive and negative edge (reverse debouncing).

The debouncing times vary (digital uncertainty). This is

caused by the asynchronism between the random input

signal and the IC clock CL.

Short circuit debouncing is shown in figure 3.

During the relay activation time, the output current is

monitored at each positive edge of the clock. In the case

of a detected short, a 3-stage shift register counts 3

negative edges.

The output stage is disabled with the following positive

edge. Depending on when the short circuit occurs, there

is a variation of 1 clock: the delay time may last from 2

to 4 clock cycles. In the case of the other times, (e.g.,

debouncimg input INT) the digital uncertainty adds up to

± 4 cycles.

Relay Output

The relay output is an open collector Darlington transistor

stage with an integrated 28-V Zener diode which limits

the relay coil‘s inductive cut–out pulse. The maximum

static collector current must not exceed 300 mA and the

saturation voltage is typically Vsat = 1.2 V@ 200 mA.

An integrated shunt resistor measures the collector

exceeded, the short circuit detection buffer is set.

The output stage is switched off and is kept disabled even

if an input switch is still on. When an input switch is

opened, the short circuit buffer is reset after the debounc-

ing delay and the output can be activated again.

If

* after closing an input switch again * a persistant

short is detected, the short circuit buffer is set again and

the output is disabled. If no short circuit condition is

detected normal operation continues.

In order to avoid short term disabling caused by current

pulses

of

transients,

a

typical

debounce

period

transistor is switched to conductive condition to prevent

it from being destroyed. The output transistor absorbs the

current during the load-dump pulse (1A, short term).

Short circuit detection is disabled during the load-dump.

Power-on Reset

When the supply voltage is switched on, an internal pow-

er-on reset pulse (POR) with a prolongation time of

logic at the condition which is defined initially.

the short circuit buffer is reset.

Functional Description

W

Interval Function

The interval mode is activated with the high side input

activated and the wiper motor performs one turn. The be-

ginning of the interval pause depends on the application

“with or without the park-switch” (see figures 5, 6, 7 and

8). If the INT switch is opened the wiper performs a full

turn as long as the relay is energized.

Contact Current and Leakage Resistance

As the current into Pin 1 (INT) only ranges from 200

mA

to 800

mA (depending on the potentiometer value), an

external pull-down resistor helps to increase the contact

current of the interval switch INT.

The input is detected “open” and the intermittent function

is not activated if the input resistance of Pin 1 exceeds

45 k

W.

During the interval pause the oscillator frequency is

approximately by using the following formulas:

[ 4.4/ (57

[ 5700

Correct operation is ensured, with

2 k

When the interval pause has been completed the oscil-