30

Multimedia ICs

BU1424K

∗ When using the RGB input mode, TEST[2] should be fixed at LOW.

∗ In the Master mode, HSYNC is output at the timing shown on the previous page. For that reason, the timing of U

and V should be determined by counting from that falling edge. In the Slave mode, the HSY, U, and V data should

be input at the timing shown on the previous page.

Table 19

TEST2

(26pin)

CLKSW

(53pin)

0

0

1

1

0

1

0

1

In a doubled clock mode, the timing of U and V is as shown in Fig. 24

In a regular clock mode, the timing of U and V is as shown in Fig. 24

In a doubled clock mode, the timing of U and V is as shown in Fig. 25

In a regular clock mode, the timing of U and V is as shown in Fig. 25

VQFP64

QFP-A64

0.15

± 0.1

48

33

32

17

49

64

1

16

14.0

± 0.2

16.4

± 0.3

0.35

± 0.1

0.8

0.15

48

33

32

17

16

1

49

64

10.0

± 0.2

12.0

± 0.3

0.2

± 0.1

0.1

0.5

0.125

± 0.1