Loss-Of-Power Logic (

LOP)

The loss-of-power logic circuitry is asserted anytime the

input power of one of the limiting amplifiers is observed

comprised of two comparators and an S-R flip-flop to

compare the outputs of the threshold-control and

power-detect circuitry for each of the limiting amplifiers

on the MAX3822. The LOP_ output corresponding to a

given input is asserted if the input power is too low. A

general LOP output is also given for the whole part; if

any LOP_ signal is low, the LOP output will also go low.

Once a LOP_ signal has been asserted, the input

power must rise above the threshold before resetting.

This prevents the LOP_ output from turning on and off

when the input signal is near the programmed thresh-

old level, an effect called chatter. The LOP_ indicator

will return to its unasserted state when the input power

level is increased (4dB typ). Figure 5 shows the output

structure.

Channel Select

The channel-select circuitry controls the operating mode

of the MAX3822 by shutting down unused amplifiers.

Single-, dual-, and quad-mode operation is programmed

by the channel-select (CS) pin. When CS is left open, the

device is placed into single-mode operation with channel

1 enabled, and channels 2, 3, and 4 disabled. Dual-

mode operation is programmed by connecting CS

2 are enabled and channels 3 and 4 are disabled. Quad-

mode operation is programmed by connecting CS

directly to GND. In quad-mode operation, all four chan-

nels are enabled. Figure 6 shows the input circuitry of

the CS pin.

Applications Information

Set Up the DC Cancellation Loop

The value of the offset-correction capacitor (CZ_)

affects the maximum speed at which the DC cancella-

tion loop can adjust to changes in DC offset at the

input. PWD and pattern-dependent jitter (PDJ) are both

error sources that can be minimized by the proper

selection of CZ_. Therefore, the loop should be as slow

as possible to reduce PDJ while performing its DC can-

cellation function. Select the CZ_ capacitor to set the

bandwidth of the DC cancellation loop. The input

impedance between CZ+ and CZ- is approximately

10k

Ω. This impedance is in series with CZ_. Therefore,

the low-frequency cutoff (foc) associated with the DC

offset-correction loop is computed as follows:

+3.3V, 2.5Gbps Quad Limiting Amplifier

_______________________________________________________________________________________

9

VTH

GND

GND

ESD

DIODES

Figure 4. Threshold Set Structure

ESD

DIODES

LOP

18k

Ω

4k

Ω

2k

Ω

GND

Figure 5. TTL Output Structure