Product Specification
Low-Power Green-Mode PWM Flyback Power Controller without Secondary Feedback
SG6849
© System General Corp.
- 10 -
www.sg.com.tw
Version 1.0(IRO33.0002.B3)
Dec.29, 2003
propagation delay TPD. This propagation delay will
introduce
an
additional
current
proportional
to
TPD*VIN/LP. The propagation delay is nearly constant
regardless of the input line voltage VIN. Higher input line
voltages will result in larger additional currents. Thus,
under high input-line voltages the output power limit will
be higher than under low input-line voltages.
Over a wide range of AC input voltages, the variation can
be significant. To compensate for this, the threshold
voltage is adjusted by adding a positive ramp. This ramp
signal can vary from 0.77V to 1.05V for SG6849-65 and
0.70 to 1.03V for SG6849-100, and it flattens out at 1.05V
and 1.03V respectively. A smaller threshold voltage
forces the output GATE drive to terminate earlier, thus
reducing total PWM turn-on time and making the output
power equal to that of the low line input. This proprietary
internal compensation feature ensures a constant output
power limit over a wide range of AC input voltages
(90VAC to 264VAC).
Under Voltage Lockout (UVLO)
The turn-on/turn-off thresholds of the SG6849 are fixed
internally at 17V/8V. To enable the SG6849 during
startup, the hold-up capacitor must first be charged to 17V
through the startup resistor.
The hold-up capacitor will continue to supply VDD before
energy can be delivered from the auxiliary winding of the
main transformer. VDD must not drop below 8V during
this startup process. This UVLO hysteresis window
ensures that the hold-up capacitor can adequately supply
VDD during startup.
Gate Output
The SG6849 BiCMOS output stage is a fast totem pole
gate driver. Cross-conduction has been avoided to
minimize heat dissipation, increase efficiency, and
enhance reliability. The output driver is clamped by an
internal 16.7V Zener diode in order to protect the power
MOSFET transistors against any harmful over-voltage
gate signals.
Slope Compensation
The sensed voltage across the current sense resistor is
used for current mode control and pulse-by-pulse current
limiting. The built-in slope compensation function
improves power supply stability. Furthermore, it prevents
sub-harmonic oscillations that normally would occur
because of peak current mode control. A positively sloped,
synchronized ramp is activated by the SG6849 with every
switching cycle. The slope of the ramp is
(max)
33
.
0
Duty
Duty
×
.
Noise Immunity
Noise from the current sense or the control signal may
cause significant pulse width jitter, particularly in
continuous-conduction mode. Slope compensation helps
alleviate this problem. Good placement and layout
practices should be followed. The designer should avoid
long PCB traces and component leads. Compensation and
filter components should be located near the SG6849.
Finally, increasing the power-MOS gate resistance is
advised.
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