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S5935TF Datasheet(PDF) 11 Page - Applied Micro Circuits Corporation |
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S5935TF Datasheet(HTML) 11 Page - Applied Micro Circuits Corporation |
11 / 190 page 1-3 ARCHITECTURAL OVERVIEW S5935 PCI Operation Registers The second group of registers are the PCI Operation Registers shown in Table 2. This group consists of sixteen 32-bit (DWORD) registers accessible to the Host processor from the PCI Local bus. These are the main registers through which the PCI Host configures S5935 operation and communicates with the Add-On Local bus. These registers encompass the PCI bus incoming and outgoing Mailboxes, FIFO data channel, Bus Master Address and Count registers, Pass-Thru data channel registers and S5935 device Status and Control registers. Add-On Bus Operation Registers The third and last register group consists of the Add-On Operation Registers, shown in Table 3. This group of eighteen 32-bit (DWORD) registers is accessible to the Add-On Local bus. These are the main registers through which the Add-On logic configures S5935 operation and communicates with the PCI Local bus. These registers encompass the Add-On bus Mailboxes, Add- On FIFO, DMA Address/Count Registers (when Add- On initiated Bus Mastering), Pass-Thru Registers and Status/Control registers. Non-Volatile Memory Interface The S5935 contains a set of PCI Configuration Regis- ters. These registers can be initialized with default values or with designer specified values contained in an external nvRAM. The nvRAM can be either a serial (2 Kbytes, maximum) or a byte-wide device (64 Kbytes, maximum). The optional nvRAM allows the Add-On card manufac- turer to initialize the S5935 with his specific Vendor ID and Device ID numbers along with desired S5935 operation characteristics. The non-volatile memory fea- ture also provides for the Expansion BIOS and POST code (power-on-self-test) options on the PCI bus. 3 e t y B 2 e t y B 1 e t y B 0 e t y B s s e r d d A D I e c i v e DD I r o d n e Vh 0 0 s u t a t S I C Pd n a m m o C I C Ph 4 0 e d o C s s a l CD I n o i s i v e Rh 8 0 t s e T fl e S n i- tl i u Be p y T r e d a e Hr e m i T y c n e t a Le z i S e n i L e h c a Ch C 0 0 r e t s i g e R s s e r d d A e s a Bh 0 1 1 r e t s i g e R s s e r d d A e s a Bh 4 1 2 r e t s i g e R s s e r d d A e s a Bh 8 1 3 r e t s i g e R s s e r d d A e s a Bh C 1 4 r e t s i g e R s s e r d d A e s a Bh 0 2 d e v r e s e Rh 4 2 e c a p S d e v r e s e Rh 8 2 e c a p S d e v r e s e Rh C 2 s s e r d d A e s a B M O R n o i s n a p x Eh 0 3 e c a p S d e v r e s e Rh 4 3 e c a p S d e v r e s e Rh 8 3 y c n e t a L . x a Mt n a r G . n i Mn i P t p u r r r e t n Ie n i L t p u r r e t n Ih C 3 Table 1. PCI Configuration Registers s r e t s i g e R n o i t a r e p O I C P s s e r d d A t e s f f O ) 1 B M O ( 1 r e t s i g e R x o b li a M g n i o g t u Oh 0 0 ) 2 B M O ( 2 r e t s i g e R x o b li a M g n i o g t u Oh 4 0 ) 3 B M O ( 3 r e t s i g e R x o b li a M g n i o g t u Oh 8 0 ) 4 B M O ( 4 r e t s i g e R x o b li a M g n i o g t u Oh C 0 ) 1 B M I ( 1 r e t s i g e R x o b li a M g n i m o c n Ih 0 1 ) 2 B M I ( 2 r e t s i g e R x o b li a M g n i m o c n Ih 4 1 ) 3 B M I ( 3 r e t s i g e R x o b li a M g n i m o c n Ih 8 1 ) 4 B M I ( 4 r e t s i g e R x o b li a M g n i m o c n Ih C 1 ) O F I F ( ) l a n o i t c e r i d i b ( t r o P r e t s i g e R O F I Fh 0 2 ) R A W M ( r e t s i g e R s s e r d d A e t i r W r e t s a Mh 4 2 ) C T W M ( r e t s i g e R t n u o C r e f s n a r T e t i r W r e t s a Mh 8 2 ) R A R M ( r e t s i g e R s s e r d d A d a e R r e t s a Mh C 2 ) C T R M ( r e t s i g e R t n u o C r e f s n a r T d a e R r e t s a Mh 0 3 ) F E B M ( r e t s i g e R s u t a t S ll u F / y t p m E x o b li a Mh 4 3 ) R S C T N I ( r e t s i g e R s u t a t S / l o r t n o C t p u r r e t n Ih 8 3 ) R S C M ( r e t s i g e R s u t a t S / l o r t n o C r e t s a M s u Bh C 3 Table 2. PCI Operation Registers |
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