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S5935TF Datasheet(PDF) 11 Page - Applied Micro Circuits Corporation

Part # S5935TF
Description  PCI 5V Bus Master/Target Device 32-bit
Download  190 Pages
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Manufacturer  AMCC [Applied Micro Circuits Corporation]
Direct Link  http://www.amcc.com
Logo AMCC - Applied Micro Circuits Corporation

S5935TF Datasheet(HTML) 11 Page - Applied Micro Circuits Corporation

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1-3
ARCHITECTURAL OVERVIEW
S5935
PCI Operation Registers
The second group of registers are the PCI Operation
Registers shown in Table 2. This group consists of
sixteen 32-bit (DWORD) registers accessible to the
Host processor from the PCI Local bus. These are the
main registers through which the PCI Host configures
S5935 operation and communicates with the Add-On
Local bus. These registers encompass the PCI bus
incoming and outgoing Mailboxes, FIFO data channel,
Bus Master Address and Count registers, Pass-Thru
data channel registers and S5935 device Status and
Control registers.
Add-On Bus Operation Registers
The third and last register group consists of the Add-On
Operation Registers, shown in Table 3. This group of
eighteen 32-bit (DWORD) registers is accessible to the
Add-On Local bus. These are the main registers through
which the Add-On logic configures S5935 operation
and communicates with the PCI Local bus. These
registers encompass the Add-On bus Mailboxes, Add-
On FIFO, DMA Address/Count Registers (when Add-
On initiated Bus Mastering), Pass-Thru Registers and
Status/Control registers.
Non-Volatile Memory Interface
The S5935 contains a set of PCI Configuration Regis-
ters. These registers can be initialized with default
values or with designer specified values contained in an
external nvRAM. The nvRAM can be either a serial (2
Kbytes, maximum) or a byte-wide device (64 Kbytes,
maximum).
The optional nvRAM allows the Add-On card manufac-
turer to initialize the S5935 with his specific Vendor ID
and Device ID numbers along with desired S5935
operation characteristics. The non-volatile memory fea-
ture also provides for the Expansion BIOS and POST
code (power-on-self-test) options on the PCI bus.
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Table 1. PCI Configuration Registers
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Table 2. PCI Operation Registers


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