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IDT71V67702, IDT71V67902, 256K x 36, 512K x 18, 3.3V Synchronous

Commercial and Industrial Temperature Ranges

SRAMs with 2.5V I/O, Flow-Through Outputs, Single Cycle Deselect

Symbol

Pin Function

I/O

Active

Description

Address Inputs

I

N/A

Synchronous Address inputs. The address register is trigge red by a combi-nation of the

rising e dge of CLK and

ADSC

Address Status

(Cache Controller)

I

LOW

Synchronous Address Status from Cache Controller.

used to load the address registers with new addresses.

ADSP

Address Status

(Processor)

I

LOW

Synchronous Address Status from Processor.

load the address registers with new addresses.

ADV

Burst Address

Advance

I

LOW

Synchronous Address Advance.

internal burst counter, controlling burst access after the initial address is loaded. When the

inp ut is HIGH the burst counter is not incremented; that is, there is no address advance.

BWE

Byte Write Enable

I

LOW

Synchronous byte write enable gates the byte write inputs

rising ed ge of CLK then

HIGH then the byte write inputs are blocked and only

Individual Byte

Write Enables

I

LOW

Synchronous byte write enables.

Any active byte write cause s all outputs to be disabled.

CE

Chip Enable

I

LOW

Synchronous chip enable.

CLK

Clock

I

N/A

This is the clock input. All timing references for the device are made with respect to this

input.

Chip Select 0

I

HIGH

Chip Select 1

I

LOW

Synchrono us active LOW chip select.

GW

Global Write

Enable

I

LOW

Synchronous global write enable. This input will write all four 9-bit data bytes when LOW

on the rising edge of CLK.

Data Input/Output

I/O

N/A

Synchronous data input/output (I/O) pins. The data input path is registered, triggered by

the rising edge of CLK. The data output path is flow-through (no output register).

LBO

Linear Burst Order

I

LOW

Asynchro nous burst order selection input. When

sequence is selected. When

static input and must not change state while the device is operating.

OE

Output Enable

I

LOW

Asynchronous output enable. When

I/O pins if the chip is also selected. When

impedance state.

Power Supply

N/A

N/A

3.3V core power supply.

Power Supply

N/A

N/A

2.5V I/O Supply.

Ground

N/A

N/A

Ground.

NC

No Connect

N/A

N/A

NC pins are not electrically connected to the device.

ZZ

Sleep Mode

1

HIGH

Asynchronous sleep mode input. ZZ HIGH will g ate the CLK internally and power down

the IDT71V67702/7902 to its lowest power consump tion level. Data retention is guaranteed

in Sleep Mode.

5317t tbl 02

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.