Genesis Microchip
gm5020/gm5020-H Data Sheet
February 2002
C5020-DAT-01Q
viii
List of Figures
Figure 1.
gm5020 System Design Example............................................................................. 2
Figure 2.
gm5020 Pinout Diagram ........................................................................................... 5
Figure 3.
gm5020 Functional Block Diagram ......................................................................... 12
Figure 4.
TCLK connection (with Crystal Resonator)............................................................. 13
Figure 5.
TCLK parasitic capacitances .................................................................................. 14
Figure 6.
TCLK connection (with Optional Resistor) .............................................................. 15
Figure 7.
TCLK connection (with Oscillator)........................................................................... 15
Figure 8.
Internal Clock Sources............................................................................................ 16
Figure 9.
Hardware Reset...................................................................................................... 18
Figure 10.
ADC Block .............................................................................................................. 19
Figure 11.
Example Signal Terminations ................................................................................. 20
Figure 12.
Positive and negative polarity OR-type CSYNC ..................................................... 21
Figure 13.
Positive and negative polarity XOR-type CSYNC ................................................... 21
Figure 14.
Positive and negative polarity serration-type CSYNC............................................. 22
Figure 15.
Positive and negative polarity "serration with equalization”-type CSYNC ............... 22
Figure 16.
gm5020 Clock Recovery......................................................................................... 23
Figure 17.
Phase Adjustment Delay Curve .............................................................................. 24
Figure 18.
DVI Block................................................................................................................ 25
Figure 19.
ITU-R BT656 Block................................................................................................. 27
Figure 20.
Image Capture Block .............................................................................................. 28
Figure 21.
Capture Window ..................................................................................................... 29
Figure 22.
HSYNC Delay ......................................................................................................... 29
Figure 23.
Active Data Crosses HSYNC Boundary ................................................................. 30
Figure 24.
ITU-R BT656 Input.................................................................................................. 31
Figure 25.
Image Measurement Block ..................................................................................... 32
Figure 26.
ODD/EVEN Field Detection .................................................................................... 33
Figure 27.
Pixel Grab ............................................................................................................... 35
Figure 28.
Digital Color Control Blocks .................................................................................... 36
Figure 29.
YUV Color Controls ................................................................................................ 36
Figure 30.
Black / Contrast / Brightness Transfer Function...................................................... 38
Figure 31.
Input LUT and Dithering.......................................................................................... 38
Figure 32.
Frame Store Interface Blocks ................................................................................. 40
Figure 33.
FRC Required Parameters ..................................................................................... 42
Figure 34.
Scaling Block .......................................................................................................... 43
Figure 35.
Gamma Correction LUT Block ................................................................................ 44
Figure 36.
Gamma Response Curve ....................................................................................... 45
Figure 37.
Display Timing and Control Blocks ......................................................................... 46
Figure 38.
DDDS Block............................................................................................................ 46
Figure 39.
Lock Event Timing (Frame Sync Mode).................................................................. 49
Figure 40.
Display Windows and Timing.................................................................................. 50
Figure 41.
Single / Double-wide Display Data.......................................................................... 50
Figure 42.
Capture Only Mode................................................................................................. 51
Figure 43.
FRC Bypass Mode.................................................................................................. 51
Figure 44.
Scaler Bypass Mode............................................................................................... 52
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