MC54/74HC574A

High–Speed CMOS Logic Data

DL129 — Rev 6

3–3

MOTOROLA

Guaranteed Limit

Unit

v 125_C

v 85_C

– 55 to

25

_C

VCC

V

Test Conditions

Parameter

Symbol

Iin

Maximum Input Leakage Current

Vin = VCC or GND

6.0

± 0.1

± 1.0

± 1.0

µA

IOZ

Maximum Three–State Leakage

Current

Output in High–Impedance State

Vin = VIL or VIH

Vout = VCC or GND

6.0

± 0.5

± 5.0

± 10

µA

ICC

Maximum Quiescent Supply

Current (per Package)

Vin = VCC or GND

Iout = 0 µA

6.0

4.0

40

160

µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

Sb l

P

T

C

di i

V

Guaranteed Limit

Ui

Symbol

Parameter

Test Conditions

VCC

V

– 55 to

25

_C

v 85_C

v 125_C

Unit

IOZ

Maximum Three–State Leakage

Current

Output in High–Impedance State

Vin = VIL or VIH

Vout = VCC or GND

6.0

± 0.5

± 5.0

± 10

µA

ICC

Maximum Quiescent Supply

Current (per Package)

Vin = VCC or GND

|Iout| = 0 µA

6.0

4.0

40

160

µA

Sb l

P

V

Guaranteed Limit

Ui

Symbol

Parameter

VCC

V

– 55 to

25

_C

v 85_C

v 125_C

Unit

fmax

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 4)

2.0

3.0

4.5

6.0

6.0

15

30

35

4.8

10

24

28

4.0

8.0

20

24

MHz

tPLH,

tPHL

Maximum Propagation Delay, Clock to Q

(Figures 1 and 4)

2.0

3.0

4.5

6.0

160

105

32

27

200

145

40

34

240

190

48

41

ns

tPLZ,

tPHZ

Maximum Propagation Delay, Output Enable to Q

(Figures 2 and 5)

2.0

3.0

4.5

6.0

150

100

30

26

190

125

38

33

225

150

45

38

ns

tPZL,

tPZH

Maximum Propagation Delay, Output Enable to Q

(Figures 2 and 5)

2.0

3.0

4.5

6 0

140

90

28

24

175

120

35

30

210

140

42

36

ns

tTLH,

tTHL

Maximum Output Transition Time, any Output

(Figures 1 and 4)

2.0

3.0

4.5

6.0

60

27

12

10

75

32

15

13

90

36

18

15

ns

Cin

Maximum Input Capacitance

10

10

10

pF

Cout

Maximum Three–State Output Capacitance, Output in High–Impedance State

15

15

15

pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–

Speed CMOS Data Book (DL129/D).

C

P

Di

i

i

C

i

(P

E

bl d O

)*

Typical @ 25

°C, VCC = 5.0 V

F

CPD

Power Dissipation Capacitance (Per Enabled Output)*

24

pF

* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).