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| KM641001A |
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 SAMSUNG
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2 page 
KM641001A CMOS SRAM PRELIMINARY Rev 5.0 - 2 - February 1998 256K x 4 Bit (with OE)High-Speed CMOS Static RAM GENERAL DESCRIPTION FEATURES • Fast Access Time 15, 20ns(Max.) • Low Power Dissipation Standby (TTL) : 25mA(Max.) (CMOS) : 8mA(Max.) Operating KM641001A - 15 : 125mA(Max.) KM641001A - 20 : 120mA(Max.) • Single 5.0V ±10% Power Supply • TTL Compatible Inputs and Outputs • I/O Compatible with 3.3V Device • Fully Static Operation - No Clock or Refresh required • Three State Outputs • Standard Pin Configuration KM641001AJ : 28-SOJ-400A PIN FUNCTION Pin Name Pin Function A0 - A17 Address Inputs WE Write Enable CS Chip Select OE Output Enable I/O1 ~ I/O4 Data Inputs/Outputs VCC Power(+5.0V) VSS Ground N.C No Connection The KM641001A is a 1,048,576-bit high-speed Static Random Access Memory organized as 262,144 words by 4 bits. The KM641001A uses 4 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNG ′s advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The KM641001A is packaged in a 400 mil 28-pin plastic SOJ. PIN CONFIGURATION(Top View) Clk Gen. I/O1 ~ I/O4 CS WE OE FUNCTIONAL BLOCK DIAGRAM Data Cont. Column Select CLK Gen. Pre-Charge Circuit Memory Array 512 Rows 512x4 Columns I/O Circuit & SOJ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vcc A17 A16 A15 A14 A13 A12 A11 N.C I/O4 I/O3 I/O2 I/O1 WE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 CS OE Vss A0 A11 A13 A15 A17 A1 A12 A14 A16 A2 A3 A4 A5 A6 A7 A8 A9 A10 |
